FinFET gate structure and method for fabricating the same

1. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor fin on the semiconductor substrate; and

a n-type gate structure over the first semiconductor fin, wherein the n-type gate structure comprises:

a first initial layer over the first semiconductor fin;

a first high-k dielectric layer over the first initial layer and enclosed by a first gate spacer;

a n-type work function metal layer over the first high-k dielectric layer, wherein an atomic concentration of a metal within a first region of the n-type work function metal layer is different than an atomic concentration of the metal within a second region of the n-type work function metal layer;

a first blocking metal layer over the n-type work function metal layer; and

a first metal filler peripherally enclosed by the first blocking metal layer.

2. The semiconductor device of claim 1 , wherein the first high-k dielectric layer is in contact with a sidewall of the first gate spacer.

3. The semiconductor device of claim 2 , wherein the first initial layer is in contact with the sidewall of the first gate spacer.

4. The semiconductor device of claim 1 , wherein the n-type work function metal layer comprises TiAl.

5. The semiconductor device of claim 1 , wherein the metal is aluminum.

6. The semiconductor device of claim 1 , wherein the first region corresponds to a first surface region facing the first blocking metal layer.

7. The semiconductor device of claim 1 , wherein:

an atomic concentration of the metal within a third region of the n-type work function metal layer is different than the atomic concentration of the metal within the second region of the n-type work function metal layer, and

the second region is between the first region and the third region.

8. The semiconductor device of claim 7 , wherein:

the first region corresponds to a first surface region facing the first blocking metal layer, and

the third region corresponds to a second surface region facing the first high-k dielectric layer.

9. The semiconductor device of claim 8 , wherein:

the n-type work function metal layer comprises a TiAl, and

the metal is aluminum.

10. The semiconductor device of claim 1 , comprising:

a p-type gate structure over a second semiconductor fin, wherein the p-type gate structure comprises a p-type work function metal layer over the second semiconductor fin.

11. The semiconductor device of claim 10 , comprising:

a TiN layer between the first high-k dielectric layer and the n-type work function metal layer, wherein the TiN layer has a same composition as the p-type work function metal layer.

12. The semiconductor device of claim 10 , wherein the p-type gate structure comprises a TiAl layer, wherein the n-type work function metal layer has a same composition as the TiAl layer.

13. The semiconductor device of claim 1 , wherein the n-type gate structure comprises a capping metal layer disposed between the first high-k dielectric layer and the n-type work function metal layer.

14. The semiconductor device of claim 13 , wherein the n-type gate structure comprises a barrier metal layer disposed between the capping metal layer and the n-type work function metal layer.

15. The semiconductor device of claim 14 , wherein the n-type gate structure comprises a TiN layer disposed between the barrier metal layer and the n-type work function metal layer.

16. The semiconductor device of claim 15 , wherein the capping metal layer comprises TiN and the barrier metal layer comprises tantalum nitride.

17. A method for forming a semiconductor device, the method comprising:

forming a first semiconductor fin on a semiconductor substrate;

forming a first initial layer over the first semiconductor fin;

forming a first high-k dielectric layer over the first initial layer, wherein the first high-k dielectric layer is enclosed by a first gate spacer;

forming a n-type work function metal layer over the first high-k dielectric layer, wherein an atomic concentration of a metal within a first region of the n-type work function metal layer is different than an atomic concentration of the metal within a second region of the n-type work function metal layer; and

forming a first blocking metal layer over the n-type work function metal layer, wherein a first metal filler is peripherally enclosed by the first blocking metal layer.

18. The method of claim 17 , comprising:

forming a TiN layer over the first high-k dielectric layer before forming the n-type work function metal layer.

19. The method of claim 17 , comprising:

forming an etch stop layer over the first gate spacer before forming the first initial layer.

20. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor fin on the semiconductor substrate and a second semiconductor fin on the semiconductor substrate; and

a n-type gate structure over the first semiconductor fin and a p-type gate structure over the second semiconductor fin, wherein each of the n-type gate structure and the p-type gate structure comprise:

a first initial layer over the first semiconductor fin;

a first high-k dielectric layer over the first initial layer and enclosed by a first gate spacer;

a TiN layer over the first high-k dielectric layer;

a TiAl layer over the TiN layer;

a first blocking metal layer over the TiAl layer; and

a first metal filler peripherally enclosed by the first blocking metal layer.