Semiconductor device and method

1. A device comprising:

first nanostructures;

a gate dielectric on the first nanostructures; and

a first gate electrode comprising:

a first layer on the gate dielectric, the first layer comprising an n-type work function metal, the first layer being disposed in an area between the first nanostructures;

a second layer on the first layer, the second layer comprising a barrier material, the barrier material being different from the n-type work function metal, the area between the first nanostructures being free of the second layer; and

a third layer on the second layer, the third layer comprising a p-type work function metal, the p-type work function metal being different from the n-type work function metal, the p-type work function metal being different from the barrier material.

2. The device of claim 1 further comprising:

a fill layer on the third layer.

3. The device of claim 2 further comprising:

a first glue layer between the third layer and the fill layer.

4. The device of claim 1 further comprising:

a first source/drain region adjacent the first nanostructures, the first source/drain region comprising n-type impurities.

5. The device of claim 1 further comprising:

second nanostructures;

the gate dielectric on the second nanostructures; and

a second gate electrode comprising:

the third layer on the gate dielectric, the third layer being disposed in an area between the second nanostructure.

6. The device of claim 5 further comprising:

a second source/drain region adjacent the second nanostructures, the second source/drain region comprising p-type impurities.

7. The device of claim 1 , wherein the second layer comprises amorphous silicon.

8. The device of claim 1 , wherein the second layer comprises tantalum nitride.

9. The device of claim 1 , wherein the second layer comprises fluorine-free tungsten.

10. A method comprising:

forming a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;

forming first source/drain regions adjacent the first channel region of the first set of nanostructures;

forming a first gate dielectric on the first channel region;

forming a first work function tuning layer on the first gate dielectric;

forming a barrier layer on the first work function tuning layer;

forming a second work function tuning layer on the barrier layer;

performing a treatment process on the second work function tuning layer to modify a second work function of the second work function tuning layer; and

depositing a fill layer on the treated second work function tuning layer.

11. The method of claim 10 further comprising:

forming a glue layer on the treated second work function tuning layer, the fill layer being deposited on the fill layer.

12. The method of claim 10 , wherein the barrier layer inhibits modification of a first work function of the first work function tuning layer during the treatment process.

13. The method of claim 10 , wherein the treatment process comprises a fluorination treatment process.

14. The method of claim 10 , wherein the treatment process comprises an oxidation treatment process.

15. The method of claim 10 further comprising:

forming a second set of nanostructures on the substrate, the second set of nanostructures comprising a second channel region;

forming a second gate dielectric layer on the second channel region;

forming the first work function tuning layer on the second gate dielectric layer;

forming the barrier layer on the first work function tuning layer on the second gate dielectric layer;

removing the barrier layer and the first work function tuning layer from the second gate dielectric layer; and

forming the second work function tuning layer on the second gate dielectric layer.

16. The method of claim 10 , wherein the barrier layer comprises amorphous silicon, tantalum nitride, or fluorine-free tungsten.

17. The method of claim 10 , wherein the first work function tuning layer is between respective portions of the first gate dielectric.

18. A method comprising:

forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and the second set of nanostructures comprising a second channel region;

forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region;

forming a n-type work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer, the n-type work function tuning layer wrapping around each of the first set of nanostructures;

forming a first barrier layer on the n-type work function tuning layer;

removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;

forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer;

performing a treatment process on the p-type work function tuning layer to modify a work function of the p-type work function tuning layer; and

forming a fill layer on the p-type work function tuning layer.

19. The method of claim 18 , wherein the treatment process comprises a fluorination treatment process.

20. The method of claim 18 , wherein the treatment process comprises an oxidation treatment process.