IP Library › Granted Patent US 11,605,635
Granted Patent B2
US 11,605,635 · App. 17/186,293 · Granted Mar 14, 2023

Semiconductor device and method of forming same

Inventors: Szu-Ying Chen (Hsinchu, TW); Sen-Hong Syue (Zhubei, TW); Li-Ting Wang (Hsinchu, TW); Huicheng Chang (Tainan, TW); Yee-Chia Yeo (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/0924H01L21/823431H01L29/0649H01L29/66795H01L29/7851
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Quick Facts
Patent No.
US 11,605,635
App. No.
17/186,293
Granted
Mar 14, 2023
Kind
B2
Abstract

In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

Claims (45)

1. A method, comprising:

forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin;

forming a first insulation material adjacent to the plurality of fins;

reducing a thickness of the first insulation material, wherein reducing the thickness of the first insulation material comprises:

modifying a first strain in the first fin at a first boundary between the first fin and the substrate; and

modifying a second strain in the second fin at a second boundary between the second fin and the substrate;

after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and

recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

2. The method of claim 1 further comprising, before forming the first insulation material, forming a liner layer adjacent to the plurality of fins.

3. The method of claim 2 , wherein forming the first insulation material comprises oxidizing the liner layer.

4. The method of claim 1 , wherein forming the first insulation material comprises conformally depositing the first insulation material.

5. The method of claim 1 , wherein the modifying the second strain is by a lesser degree than the modifying the first strain.

6. The method of claim 1 , wherein recessing the first insulation material and the second insulation material further comprises forming a second STI region, wherein the first STI region comprises the first insulation material and the second insulation material, and wherein the second STI region comprises the first insulation material and is free of the second insulation material.

7. The method of claim 1 , wherein reducing the thickness of the first insulation material comprises performing an anneal on the first insulation material.

8. A method, comprising:

forming a first fin, a second fin, and a third fin adjacent to a substrate, the first fin and the second fin separated by a first opening, the second fin and the third fin separated by a second opening;

depositing a first insulation material in the first opening and in the second opening, a first portion of the first insulation material in the first opening and proximal to the substrate having a first thickness, a second portion of the first insulation material in the first opening and along a sidewall of the second fin having a second thickness;

annealing the first insulation material, wherein after the annealing the first insulation material:

the first portion has a third thickness, the third thickness being less than the first thickness;

the second portion has a fourth thickness, the fourth thickness being less than the second thickness; and

the first insulation material applies a first compressive stress on the first fin and a second compressive stress on the second fin;

forming a second insulation material adjacent to the first insulation material;

recessing the first insulation material and the second insulation material to form a first isolation region and a second isolation region; and

forming gate structures adjacent to the first fin, the second fin, and the third fin.

9. The method of claim 8 , wherein the first compressive stress causes a greater strain in a lower portion of the first fin as compared to an upper portion of the first fin, the lower portion being more proximal than the upper portion to the substrate.

10. The method of claim 8 , wherein the third thickness is about 80-95% of the first thickness, and wherein the fourth thickness is about 80-95% of the second thickness.

11. The method of claim 8 , wherein after depositing the first insulation material, the first insulation material fills a portion of the first opening and an entirety of the second opening.

12. The method of claim 11 , wherein after depositing the second insulation material, the second insulation material fills a remainder of the first opening.

13. The method of claim 8 further comprising, before depositing the first insulation material, forming a liner layer in the first opening and in the second opening.

14. The method of claim 13 , wherein during the depositing the first insulation material, the liner layer becomes nitridized.

15. The method of claim 8 , wherein before the annealing, the first insulation material comprises nitrogen, oxygen, and carbon.

16. A method, comprising:

forming first semiconductor fins and second semiconductor fins over a substrate, the first semiconductor fins comprising a first fin and a second fin, the second semiconductor fins comprising a third fin, a fourth fin, and a fifth fin, a first opening being disposed between the first semiconductor fins and the second semiconductor fins, a second opening being disposed between the third fin and the fourth fin, a third opening being disposed between the fourth fin and the fifth fin;

depositing a first insulation material over the first semiconductor fins and the second semiconductor fins, the first insulation material filling entireties of the second opening and the third opening;

reducing a thickness of a first portion of the first insulation material, the first portion of the first insulation material being disposed in the first opening and extending from the second fin to the third fin, wherein reducing the thickness of the first portion of the first insulation material forms a first strain in a lower region of the third fin and a second strain in a lower region of the fourth fin;

depositing a second insulation material over the first semiconductor fins and the second semiconductor fins, the second insulation material filling a remainder of the first opening;

planarizing the second insulation material to be level with the first insulation material; and

etching the first insulation material and the second insulation material to form:

a first isolation region disposed between the first semiconductor fins and the second semiconductor fins;

a second isolation region disposed between the third fin and the fourth fin; and

a third isolation region disposed between the fourth fin and the fifth fin.

17. The method of claim 16 , wherein the first strain has a greater absolute value than the second strain.

18. The method of claim 16 , further comprising, before depositing the first insulation material, forming a liner layer over the first semiconductor fins and the second semiconductor fins.

19. The method of claim 18 , wherein during the depositing the first insulation material, the liner layer becomes oxidized.

20. The method of claim 16 , wherein the first strain in the lower region of the third fin is a first compressive strain, wherein the second strain in the lower region of the fourth fin is a second compressive strain, and wherein the first compressive strain is greater than the second compressive strain.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2021
From: CHEN, SZU-YING; SYUE, SEN-HONG; WANG, LI-TING; CHANG, HUICHENG; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 055960/0837 →
Continuity (1)
Related Publication 20220278097A1 · Sep 1, 2022