Wafer on wafer bonding structure

1. A method comprising:

thinning a first wafer to expose metal vias;

forming a bonding layer over the metal vias, the metal vias extending through the bonding layer;

positioning a second wafer to the first wafer, wherein bond pads of the second wafer align to the metal vias of the first wafer;

bonding the bond pads of the second wafer with the metal vias of the first wafer without using a bonding material between the bond pads and the metal vias;

fusing the bonding layer of the first wafer to a bonding layer of the second wafer, to form a first wafer stack;

positioning the first wafer stack to a third wafer, wherein bond pads of the first wafer align to metal features of the third wafer;

bonding the bond pads of the first wafer with the metal features of the third wafer without using a bonding material between the bond pads and the metal features; and

fusing a bonding layer of the first wafer to a bonding layer of the third wafer.

2. The method of claim 1 , wherein forming the bonding layer comprises:

recessing a first material surrounding the metal vias;

depositing a second material corresponding to the bonding layer; and

planarizing the second material to level an upper surface of the second material with upper surfaces of the metal vias.

3. The method of claim 1 , wherein forming the bonding layer comprises:

depositing the bonding layer over the metal vias;

forming openings in the bonding layer, the openings corresponding to the metal vias;

depositing a metal via extension in the openings, the metal via extension being physically coupled to the metal vias; and

planarizing the metal via extension to level an upper surface of the bonding layer with upper surfaces of the metal via extensions.

4. The method of claim 1 , wherein the first wafer comprises a controller for controlling devices in the first wafer stack.

5. The method of claim 1 , wherein the first wafer is face down and the third wafer is face up, a face of the third wafer being bonded to a face of the first wafer.

6. The method of claim 1 , wherein the bonding layer of the first wafer is between 0.8 μm and 3 μm thick.

7. The method of claim 1 , wherein the first wafer and second wafer together form a first wafer stack, further comprising:

forming a second wafer stack comprising a two-layer wafer stack, the two-layer wafer stack including the third wafer;

thinning the second wafer to expose second metal vias of the first wafer stack;

forming a second bonding layer over the second metal vias, the second metal vias extending through the second bonding layer;

positioning the second wafer stack to the first wafer stack, wherein bond pads of the second wafer stack align to the second metal vias;

bonding the bond pads of the second wafer stack with the second metal vias of the first wafer stack without using a bonding material between the bond pads of the second wafer stack and the second metal vias; and

fusing the second bonding layer to a bonding layer of the second wafer stack to form a first four-level wafer stack.

8. The method of claim 7 , further comprising:

positioning the first four-level wafer stack to a fourth wafer, wherein bond pads of the first four-level wafer stack align to metal features of the fourth wafer;

bonding the bond pads of the first four-level wafer stack with the metal features of the fourth wafer without using a bonding material between the bond pads and the metal features; and

fusing a bonding layer of the first four-level wafer stack to a bonding layer of the fourth wafer.

9. The method of claim 7 , wherein each wafer in the first four-level wafer stack are face down.

10. A method comprising:

forming a first bonding layer on a backside of a first wafer, comprising:

recessing the backside of the first wafer to expose a first via of the first wafer, a portion of the first via protruding from the backside of the first wafer,

depositing the first bonding layer, and

planarizing the first bonding layer to level an upper surface of the first via with an upper surface of the first bonding layer;

fusing a second bonding layer on a front side of a second wafer to the first bonding layer of the first wafer;

forming a third bonding layer on a backside of the second wafer; and

fusing a fourth bonding layer on a front side of a third wafer to the third bonding layer.

11. The method of claim 10 , wherein the first bonding layer and the second bonding layer are each between 0.8 μm and 3 μm thick.

12. The method of claim 10 , further comprising bonding the first via to a corresponding contact pad of the second wafer.

13. The method of claim 10 , wherein the first wafer and second wafer together form a first two-wafer stack, further comprising:

bonding the first two-wafer stack to a second two-wafer stack to form a four-wafer stack.

14. The method of claim 10 , further comprising:

fusing a fifth bonding layer on a front side of a fourth wafer to the third wafer to form a four-wafer stack.

15. The method of claim 10 , wherein the first wafer, the second wafer, and the third wafer are part of a first wafer stack, further comprising:

bonding the first wafer stack to a device wafer; and

singulating a package device from the device wafer and first wafer stack.

16. A method comprising:

bonding a first wafer to a second wafer, comprising at a bonding interface of the first wafer and the second wafer, physically coupling metal vias of the first wafer to bond pads of the second wafer and physically fusing a first bonding layer of the first wafer to a second bonding layer of the second wafer, the first bonding layer disposed at a back side of the first wafer, the second bonding layer disposed at a front side of the second wafer, the metal vias of the first wafer traversing through the first bonding layer, through a semiconductor substrate, and through a first interconnect of the first wafer;

bonding a third wafer to the second wafer, comprising physically fusing a fourth bonding layer of the third wafer to a third bonding layer of the second wafer; and

bonding a fourth wafer to the third wafer, comprising physically fusing a sixth bonding layer of the fourth wafer to a fifth bonding layer of the third wafer.

17. The method of claim 16 , wherein each of the first wafer, second wafer, third wafer, and fourth wafer are face down.

18. The method of claim 16 , further comprising:

etching recesses in a front side of the first wafer;

forming the metal vias in the first wafer;

thinning the back side of the first wafer to expose the metal vias;

recessing the back side of the first wafer to cause the metal vias to protrude from the back side of the first wafer; and

depositing the first bonding layer to laterally surround the metal vias.

19. The method of claim 16 , further comprising:

bonding a front side of the first wafer to a device wafer to form a multi-wafer stack;

attaching the multi-wafer stack to a carrier;

forming connectors on the device wafer; and

singulating a package from the multi-wafer stack.

20. The method of claim 16 , further comprising:

forming the first bonding layer over the back side of the first wafer;

forming openings in the first bonding layer to expose through-silicon vias of the first wafer; and

forming the metal vias in the openings to extend the through-silicon vias through the first bonding layer.