Method for forming epitaxial source/drain features using a self-aligned mask and semiconductor devices fabricated thereof
Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.
1. A method for forming a semiconductor device, comprising:
forming first and second fin structures;
epitaxially growing a first source/drain feature from the first fin structure while the second fin structure is covered by a hard mask layer;
forming a self-aligned mask layer covering the first source/drain feature, wherein forming the self-aligned mask layer comprises:
forming a cap layer comprising a first element and a second element;
oxidizing at least a portion of the cap layer; and
annealing the oxide layer to remove at least a portion of the second element:
removing the hard mask layer covering the second fin structure;
epitaxially growing a second source/drain feature from the second fin structure;
removing the self-aligned mask layer;
depositing a contact etch stop layer to cover the first and second source/drain features; and
depositing an interlayer dielectric material over the contact etch stop layer.
2. The method of claim 1 , wherein forming the self-aligned mask layer comprising:
epitaxially growing a liner on the first source/drain feature; and
epitaxially growing the cap layer over on the liner.
3. The method of claim 2 , wherein the liner includes the first element, and the cap layer includes the first element and the second element.
4. The method of claim 3 , wherein oxidizing at least a portion of the cap layer is performed by decoupled plasma oxidation.
5. The method of claim 3 , wherein the first element is silicon and the second element is geranium.
6. The method of claim 3 , wherein the first element is silicon and second element is phosphorus.
7. The method of claim 1 , wherein removing the second element comprises performing an anneal process in a nitrogen environment.
8. A method for forming a semiconductor device, comprising:
forming a first source/drain feature comprising a first element;
selectively forming an epitaxial liner on the first source/drain feature, wherein the epitaxial liner comprises the first element and a second element;
oxidizing a portion of the epitaxial liner to form a mask layer;
removing at least a portion of the second element from the epitaxial liner;
forming a second source/drain feature while the first source/drain features is covered by the epitaxial liner, wherein the second source/drain feature comprises the second element; and
depositing a contact etch stop layer over the first and second source/drain features, wherein the contact etch stop layer is formed directly on the second source/drain feature, and the epitaxial liner is disposed between the first source/drain feature and the contact etch stop layer.
9. The method of claim 8 , wherein the epitaxial liner comprises an epitaxially semiconductor layer.
10. The method of claim 9 , wherein the first element is silicon.
11. The method of claim 10 , wherein forming the epitaxial liner comprises:
forming a first semiconductor liner comprising the first element;
forming a semiconductor cap layer comprising the second element over the first semiconductor liner.
12. The method of claim 11 , wherein the second element comprises geranium.
13. The method of claim 11 , further comprising:
removing the mask layer prior to depositing the contact etch stop layer, wherein a portion of the mask layer is in contact with the second source/drain feature.
14. The method of claim 13 , wherein oxidizing the epitaxial liner comprises oxidizing the semiconductor cap layer.
15. The method of claim 8 , wherein the first source/drain feature is a source/drain feature for a N-type device and the second source/drain feature is a source/drain feature for a P-type device.
16. A method for forming a semiconductor device, comprising:
forming a first source/drain feature, wherein the first source/drain feature comprising one or more first elements for a first type of devices;
forming a self-aligned liner on the first source/drain feature, wherein the self-aligned liner comprises:
a first liner layer in contact with the first source/drain feature, wherein the first layer comprises an epitaxial semiconductor layer;
a second liner layer in contact with the first liner layer, wherein the second liner layer comprises one or more second elements for a second type of devices; and
oxidizing the self-aligned liner;
removing at least a portion of the one or more second elements from the self-aligned liner;
forming a second source/drain feature while the first source/drain feature is covered by the self-aligned liner, wherein the second source/drain feature comprises one or more the second elements for the second type of devices; and
depositing a contact etch stop layer over the self-aligned liner and the second source/drain feature.
17. The method of claim 16 , wherein oxidizing the self-aligned liner comprises forming a third liner layer in contact with the second liner layer.
18. The method of claim 16 , wherein removing one or more second elements comprises performing an anneal process in a nitrogen environment.
19. The method of claim 16 , wherein oxidizing at least a portion of the self-aligned layer is performed by decoupled plasma oxidation.
20. The method of claim 16 , wherein the first type of devices are N-type devices.