Interconnects on multiple sides of a semiconductor structure
A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.
1. A semiconductor structure comprising:
a front-end-of-line region comprising two or more devices;
a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region;
a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region; and
one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.
2. The semiconductor structure of claim 1 , wherein at least one of the one or more passthrough vias is self-aligned to at least one of the two or more devices in the front-end-of-line region.
3. The semiconductor structure of claim 1 , wherein at least one of the one or more passthrough vias is self-aligned to one or more dummy gate structures in the front-end-of-line region.
4. The semiconductor structure of claim 1 , wherein at least one of the one or more passthrough vias is disposed in a device to device boundary between first and second ones of the two or more devices in the front-end-of-line region.
5. The semiconductor structure of claim 1 , wherein the first set of interconnects are arranged in two or more wiring layers in the first back-end-of-line region, and wherein the two or more wiring layers in the first back-end-of-line region provide at least one of power and wire routing for at least the first subset of the two or more devices in the front-end-of-line region.
6. The semiconductor structure of claim 5 , wherein the second set of interconnects are arranged in a wiring layer in the second back-end-of-line region, and wherein the wiring layer provides a power rail for at least the second subset of the two or more devices in the front-end-of-line region.
7. The semiconductor structure of claim 5 , wherein the second set of interconnects are arranged in two or more wiring layers in the second back-end-of-line region, and wherein the two or more wiring layers in the second back-end-of-line region provide at least one of power and wire routing for at least the second subset of the two or more devices in the front-end-of-line region.
8. The semiconductor structure of claim 1 , wherein the two or more devices in the front-end-of-line region comprise at least one of fin field-effect transistors and nanosheet transistors.