Apparatuses and methods for parallel writing to multiple memory device structures
The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
1. A method, comprising:
setting a series of registers in a bank arbiter to mask bank address bits and row address bits for a plurality of locations in a plurality of banks;
receiving a multicast write command to a bank of the plurality of banks; and
dispatching resolved instructions and/or constant data to the bank in order to write to the plurality of locations in parallel.
2. The method of claim 1 , further comprising:
receiving resolved instructions and/or constant data to the bank of a dynamic random access memory array (DRAM); and
performing the multicast data write operation to a plurality of subarrays to the DRAM.
3. The method of claim 1 , further comprising receiving an augmented DRAM write command to indicate when writes are to be performed in a multicast manner.
4. The method of claim 1 , further comprising performing the multicast data write operation using a DRAM write path.
5. The method of claim 1 , further comprising reading the series of registers in association with performing a multicast write operation.
6. The method of claim 1 , further comprising:
setting the series of registers to mask odd numbered subarrays in even numbered banks; and
setting the series of registers to mask even numbered subarrays in odd numbered banks.
7. The method of claim 1 , further comprising:
receiving the multicast write command to the bank arbiter in a plurality of memory devices from a channel controller, wherein the resolved instructions and/or constant data are pre-resolved by the channel controller;
reading the series of registers set in each of the bank arbiters;
performing the multicast data write operation in parallel to resolved locations in the plurality of banks in the plurality of memory devices and to resolved locations in a plurality of subarrays in respective banks using a dynamic random access memory (DRAM) write path.
8. The method of claim 7 , further comprising using a first resolved location for the plurality of subarrays, separate from a second resolved location of the plurality of banks.
9. An apparatus, comprising:
a memory comprising a plurality of banks; and
a bank arbiter coupled to the plurality of banks and comprising a series of registers, wherein the bank arbiter is configured to:
set the series of registers to mask bank address bits and row address bits for a plurality of locations in the plurality of banks;
receive a multicast write command to a bank of the plurality of banks; and
dispatch resolved instructions and/or constant data to the bank in order to write to the plurality of locations in parallel.
10. The apparatus of claim 9 , wherein the memory comprises a dynamic random access memory array (DRAM).
11. The apparatus of claim 9 , wherein the bank arbiter is configured to receive an augmented DRAM write command to indicate when writes are to be performed in a multicast manner.
12. The apparatus of claim 9 , wherein the bank arbiter is configured to perform the multicast data write operation using a DRAM write path.
13. The apparatus of claim 9 , wherein the bank arbiter is configured to:
set the series of registers to mask odd numbered subarrays in even numbered banks; and
set the series of registers to mask even numbered subarrays in odd numbered banks.
14. The apparatus of claim 9 , wherein the bank arbiter is configured to:
receive the multicast write command from a channel controller, wherein the resolved instructions and/or constant data are pre-resolved by the channel controller;
read the series of registers set in the bank arbiter; and
perform the multicast data write operation in parallel to resolved locations in the plurality of banks using a dynamic random access memory (DRAM) write path.
15. The apparatus of claim 14 , wherein the bank arbiter is configured to use a first resolved location for the plurality of subarrays, separate from a second resolved location of the plurality of banks.