IP Library › Granted Patent US 12,255,278
Granted Patent B2
US 12,255,278 · App. 17/198,039 · Granted Mar 18, 2025

Semiconductor light emitting element and semiconductor light emitting device

Inventors: Yasumitsu Kunoh (Toyama, JP); Masahiro Kume (Toyama, JP); Masanori Hiroki (Shiga, JP); Keimei Masamoto (Niigata, JP); Toshiya Fukuhisa (Osaka, JP); Shigeo Hayashi (Kyoto, JP)
Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
H01L33/647H01L24/14H01L33/62H01L2224/14519H01L2924/12041H01L2933/0066H01L2933/0075
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,255,278
App. No.
17/198,039
Granted
Mar 18, 2025
Kind
B2
Abstract

A semiconductor light emitting element includes: a substrate; an n-type layer; a light emitting layer; a p-type layer; a p electrode located above the p-type layer; an n electrode located in a region that is above the n-type layer and in which the light emitting layer and the p-type layer are not located; a p-electrode bump connected to the p electrode; an n-electrode bump connected to the n electrode; and an insulation bump located in at least one of a region between the n-electrode bump and the p-type layer and a region whose distance from an end of the p-type layer closer to the n-electrode bump is shorter than a distance from the end to the p-electrode bump, in a plan view of the substrate. A surface of the insulation bump opposite to a surface facing the substrate is insulated from the p electrode and the n electrode.

Claims (41)

1. A semiconductor light emitting device, comprising:

a semiconductor light emitting element; and

a mounting substrate, wherein:

the semiconductor light emitting element includes:

a substrate;

an n-type layer located above the substrate and including an n-type semiconductor;

a light emitting layer located above the n-type layer;

a p-type layer located above the light emitting layer and including a p-type semiconductor;

a p electrode located above the p-type layer;

an n electrode located in a region that is above the n-type layer and in which the light emitting layer and the p-type layer are not located;

a conductive p-electrode bump located above the p electrode and electrically connected to the p electrode;

a conductive n-electrode bump located above the n electrode and electrically connected to the n electrode; and

an insulation bump located in at least one region selected from a region between the n-electrode bump and the p-type layer and a region whose distance from an end of the p-type layer closer to the n-electrode bump is shorter than a distance from the end of the p-type layer to a position at which the p-electrode bump is located, in a plan view of the substrate,

the insulation bump includes a film and a columnar conductor, in order from a side on which the substrate is located,

the film is made of a resin containing a filler, and the columnar conductor is made of Au,

the insulation bump is located above an end of the p-type layer facing the n electrode,

the mounting substrate includes a first wiring electrode electrically connected to the p-electrode bump and a second wiring electrode electrically connected to the n-electrode bump,

the insulation bump is located in a region sandwiched between the n electrode and the first wiring electrode, or in a region sandwiched between the p electrode and the second wiring electrode, and

the columnar conductor is in contact with the first wiring electrode or the second wiring electrode.

2. The semiconductor light emitting device according to claim 1 , wherein the insulation bump is located across an end of the p electrode facing the n electrode in the plan view of the substrate.

3. The semiconductor light emitting device according to claim 1 , wherein the mounting substrate further includes a third wiring electrode located between the first wiring electrode and the second wiring electrode and electrically independent of the first wiring electrode and the second wiring electrode.

4. The semiconductor light emitting device according to claim 1 , wherein the insulation bump has a width narrower than a width of a gap between the first wiring electrode and the second wiring electrode, in a section that passes the insulation bump and the n-electrode bump and is perpendicular to a main surface of the substrate.

5. A semiconductor light emitting device, comprising:

a semiconductor light emitting element; and

a mounting substrate, wherein:

the semiconductor light emitting element includes:

a substrate;

an n-type layer located above the substrate and including an n-type semiconductor;

a light emitting layer located above the n-type layer;

a p-type layer located above the light emitting layer and including a p-type semiconductor;

a p electrode located above the p-type layer;

an n electrode located in a region that is above the n-type layer and in which the light emitting layer and the p-type layer are not located;

a conductive p-electrode bump located above the p electrode and electrically connected to the p electrode;

a conductive n-electrode bump located above the n electrode and electrically connected to the n electrode; and

an insulation bump located in at least one region selected from a region between the n-electrode bump and the p-type layer and a region whose distance from an end of the p-type layer closer to the n-electrode bump is shorter than a distance from the end of the p-type layer to a position at which the p-electrode bump is located, in a plan view of the substrate,

the insulation bump includes a film and a columnar conductor, in order from a side on which the substrate is located,

the film is made of a resin containing a filler, and the columnar conductor is made of Au,

a surface of the insulation bump opposite to a surface facing the substrate is insulated from the p electrode and the n electrode, and the insulation bump is located above an end of the p-type layer facing the n electrode,

the mounting substrate includes a first wiring electrode electrically connected to the p-electrode bump and a second wiring electrode electrically connected to the n-electrode bump,

the insulation bump is located in a region sandwiched between the n electrode and the first wiring electrode, or in a region sandwiched between the p electrode and the second wiring electrode, and

in the plan view of the substrate, the insulation bump is located at an end of the p electrode facing the n electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2021
From: KUNOH, YASUMITSU; KUME, MASAHIRO; HIROKI, MASANORI; MASAMOTO, KEIMEI; FUKUHISA, TOSHIYA; HAYASHI, SHIGEO
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 055556/0058 →
Priority Claims (1)
JP 2018-171212 · Sep 13, 2018 · national
Continuity (2)
Continuation PCTJP2019035126 · Sep 6, 2019
Related Publication 20210217942A1 · Jul 15, 2021
References Cited (25)
US 7307286B2 · Ito · 2007 [cited by examiner]
US 7675755B2 · Imai · 2010 [cited by examiner]
US 9105829B2 · Tischler · 2015 [cited by examiner]
US 10177277B2 · Chu · 2019 [cited by examiner]
US 11183615B2 · Hiroki · 2021 [cited by examiner]
US 20010032985A1 · Bhat et al. · 2001 [cited by applicant]
US 20040012958A1 · Hashimoto et al. · 2004 [cited by applicant]
US 20050082691A1 · Ito · 2005 [cited by examiner]
US 20050194605A1 · Shelton et al. · 2005 [cited by applicant]
US 20080101071A1 · Imai · 2008 [cited by examiner]
US 20100252855A1 · Kamei · 2010 [cited by applicant]
US 20130248916A1 · Suehiro et al. · 2013 [cited by applicant]
US 20140264427A1 · Tischler · 2014 [cited by applicant]
JP 2001203386A · 2001 [cited by applicant]
JP 2002042525A · 2002 [cited by applicant]
JP 2003110148A · 2003 [cited by applicant]
JP 2007527123A · 2007 [cited by applicant]
JP 2008135694A · 2008 [cited by applicant]
JP 2013179373A · 2013 [cited by applicant]
JP 2013225646A · 2013 [cited by applicant]
WO 02089221A1 · 2002 [cited by applicant]
WO 2005091848A2 · 2005 [cited by applicant]
WO 2009063638A · 2009 [cited by applicant]
Japanese Office Action dated May 16, 2023 issued in the corresponding Japanese Patent Application No. 2020-545980. [cited by applicant]
International Search Report (ISR) issued on Dec. 10, 2019 in International (PCT) Application No. PCT/JP2019/035126, with English translation. [cited by applicant]