IP Library Granted Patent US 11,658,185
Granted Patent B2
US 11,658,185 · App. 17/198,660 · Granted May 23, 2023

Metal oxide and semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Motoki Nakashima (Atsugi, JP); Haruyuki Baba (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1225H01L29/66757H01L29/7869H01L29/78648H01L29/78693H01L29/78696G02F1/1368G02F1/136222G02F2201/44
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Quick Facts
Patent No.
US 11,658,185
App. No.
17/198,660
Granted
May 23, 2023
Kind
B2
Abstract

A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum lower than that of the first region. The second region comprises more carriers than the first region. A difference between the energy level of the conduction band minimum of the first region and the energy level of the conduction band minimum of the second region is 0.2 eV or more. The energy gap of the first region is greater than or equal to 3.3 eV and less than or equal to 4.0 eV and the energy gap of the second region is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.

Claims (60)

1. A semiconductor device comprising:

a metal oxide comprising a channel formation region, a pair of electrodes in contact with the metal oxide, an insulator in contact with the metal oxide, and a gate electrode overlapping with the channel formation region with the insulator therebetween,

wherein the metal oxide is a composite material which comprises:

a plurality of first regions formed of a first material; and

a second region formed of a second material,

wherein the first material and the second material each comprise In, Zn and O,

wherein the first material comprises Ga,

wherein a concentration of In in the second material is higher than a concentration of In in the first material,

wherein the first regions are irregularly dispersed in the second region,

wherein the concentration of In is changing gradually between the first regions and the second region so that the border between the first regions and the second region is unclear in the EDX mapping image,

wherein each of the plurality of first regions has a size of greater than or equal to 0.5 nm and less than or equal to 2 nm,

wherein an energy level of a conduction band minimum of the second material is lower than an energy level of the conduction band minimum of the first material by 0.2 eV or more,

wherein an energy gap of first material is greater than or equal to 3.3 eV and less than or equal to 4.0 eV, and

wherein an energy gap of the second material is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.

2. The semiconductor device according to claim 1 ,

wherein a carrier concentration in the second region is higher than a carrier concentration in the first regions.

3. The semiconductor device according to claim 2 ,

wherein the carrier concentration in the second region is higher than or equal to 1×10 16 cm −3 and lower than or equal to 1×10 18 cm −3 , and

the carrier concentration in the first regions is higher than or equal to 1×10 10 cm −3 and lower than or equal to 1×10 16 cm −3 .

4. The semiconductor device according to claim 1 ,

wherein the metal oxide is a single layer.

5. The semiconductor device according to claim 1 ,

wherein each of the plurality of the first regions comprises a crystal with a size greater than or equal to 1 nm and less than or equal to 2 nm, and

wherein a crystal orientation of a plurality of the crystals is irregular.

6. The semiconductor device according to claim 1 ,

wherein the second region comprises crystals with a size greater than or equal to 1 nm and less than or equal to 2 nm.

7. The semiconductor device according to claim 1 ,

wherein the second region comprises a region where the second material is amorphous.

8. A display device comprising:

a display portion comprising a pixel,

wherein the pixel comprises the semiconductor device according to claim 1 .

9. A display device comprising:

a display portion and a gate driver,

wherein the gate driver comprises the semiconductor device according to claim 1 .

10. A semiconductor device comprising:

a metal oxide film comprising a channel formation region, a pair of electrodes in contact with the metal oxide film, an insulator in contact with the metal oxide film, and a gate electrode overlapping with the channel formation region with the insulator therebetween,

wherein the metal oxide film comprises:

a plurality of first regions formed of a first material; and

a second region formed of a second material,

wherein the metal oxide film is separated into the plurality of first regions and the second region,

wherein the plurality of first regions and the second region are distributed in the metal oxide film,

wherein the first material and the second material each comprise In, Zn and 0 ,

wherein the first material comprises Ga,

wherein a concentration of In in the second material is higher than a concentration of In in the first material, and

wherein each of the plurality of first regions has a size of greater than or equal to 0.5 nm and less than or equal to 2 nm.

11. The semiconductor device according to claim 10 ,

wherein the metal oxide film is a single layer.

12. The semiconductor device according to claim 10 ,

wherein each of the plurality of the first regions comprises a crystal with a size greater than or equal to 1 nm and less than or equal to 2 nm, and

wherein a crystal orientation of a plurality of the crystals is irregular.

13. The semiconductor device according to claim 10 ,

wherein the second region comprises crystals with a size greater than or equal to 1 nm and less than or equal to 2 nm.

14. The semiconductor device according to claim 10 ,

wherein the second region comprises a region where the second material is amorphous.

15. A display device comprising:

a display portion comprising a pixel,

wherein the pixel comprises the semiconductor device according to claim 10 .

16. A display device comprising:

a display portion and a gate driver,

wherein the gate driver comprises the semiconductor device according to claim 10 .

Priority Claims (1)
JP 2016-137193 · Jul 11, 2016 · national
Continuity (3)
Continuation 16935469 · Jul 22, 2020
Continuation 15637081 · Jun 29, 2017
Related Publication 20210202538A1 · Jul 1, 2021
Cited By (1)
US 12,446,316