Memory device, integrated circuit device and method
A memory device includes a bit line, a source line, a plurality of word lines, and a memory cell. The memory cell includes a plurality of memory strings coupled in parallel between the bit line and the source line. Each of the plurality of memory strings includes a plurality of memory elements coupled in series between the bit line and the source line, and electrically coupled correspondingly to the plurality of word lines.
1. A memory device, comprising:
a bit line;
a source line;
a plurality of word lines; and
a memory cell,
wherein
the memory cell comprises a plurality of memory strings coupled in parallel between the bit line and the source line, and
each of the plurality of memory strings comprises a plurality of memory elements coupled in series between the bit line and the source line, and electrically coupled correspondingly to the plurality of word lines.
2. The memory device of claim 1 , wherein
each memory element of the plurality of memory elements of each of the memory strings is programmable to have different resistances.
3. The memory device of claim 1 , wherein
each memory element of the plurality of memory elements of each of the memory strings is individually programmable independently of other memory elements in the memory cell.
4. The memory device of claim 1 , wherein
the plurality of word lines comprises first and second word lines,
the memory cell comprises first and second memory strings,
each of the first and second memory strings comprises first and second memory elements coupled in series between the bit line and the source line, and
the first memory elements of the first and second memory strings are electrically coupled to the first word line, and the second memory elements of the first and second memory strings are electrically coupled to the second word line.
5. The memory device of claim 4 , wherein
each of the first and second memory elements of each the first and second memory strings is individually programmable to have first and second different resistances, and the memory cell is programmable to have six different total resistances.
6. The memory device of claim 4 , wherein
the first memory element of the first memory string is electrically coupled between the bit line and a first node,
the second memory element of the first memory string is electrically coupled between the first node and the source line,
the first memory element of the second memory string is electrically coupled between the source line and a second node, and
the second memory element of the second memory string is electrically coupled between the second node and the bit line.
7. The memory device of claim 6 , further comprising:
a further memory cell; and
a further source line,
wherein
the plurality of word lines comprises first and second further word lines,
the further memory cell comprises first and second further memory strings,
each of the first and second further memory strings comprises first and second further memory elements coupled in series between the bit line and the further source line, and
the first further memory elements of the first and second further memory strings are electrically coupled to the first further word line, and the second further memory elements of the first and second further memory strings are electrically coupled to the second further word line.
8. The memory device of claim 7 , wherein
the first further memory element of the first further memory string is electrically coupled between the bit line and a first further node,
the second further memory element of the first further memory string is electrically coupled between the first further node and the further source line,
the first further memory element of the second further memory string is electrically coupled between the further source line and a second further node, and
the second further memory element of the second further memory string is electrically coupled between the second further node and the bit line.
9. The memory device of claim 8 , further comprising:
a first auxiliary conductive line electrically coupled to
the first node between the first and second memory elements in the first memory string, and
the first further node between the first and second further memory elements in the first further memory string; and
a second auxiliary conductive line electrically coupled to
the second node between the first and second memory elements in the second memory string, and
the second further node between the first and second further memory elements in the second further memory string.
10. The memory device of claim 1 , further comprising:
a controller coupled to the memory cell, the controller comprising a computing-in-memory circuit configured to perform at least one mathematical or logical operation based on data read from the memory cell.
11. An integrated circuit (IC) device, comprising:
a plurality of source lines;
a plurality of word line sets each comprising first and second word lines;
a plurality of bit lines;
a plurality of auxiliary conductive line sets each comprising first and second auxiliary conductive lines; and
a plurality of memory cells each electrically coupled to
a corresponding source line among the plurality of source lines,
the first and second word lines in a corresponding word line set among the plurality of word line sets,
a corresponding bit line among the plurality of bit lines, and
the first and second auxiliary conductive lines in a corresponding auxiliary conductive line set among the plurality of auxiliary conductive line sets,
wherein each of the plurality of memory cells comprises:
a first memory element which is electrically coupled between the corresponding bit line and the corresponding first auxiliary conductive line, and has a control terminal electrically coupled to the corresponding first word line,
a second memory element which is electrically coupled between the corresponding source line and the corresponding second auxiliary conductive line, and has a control terminal electrically coupled to the corresponding first word line,
a third memory element which is electrically coupled between the corresponding source line and the corresponding first auxiliary conductive line, and has a control terminal electrically coupled to the corresponding second word line, and
a fourth memory element which is electrically coupled between the corresponding bit line and the corresponding second auxiliary conductive line, and has a control terminal electrically coupled to the corresponding second word line.
12. The IC device of claim 11 , wherein
in each of the plurality of memory cells,
each of the first through fourth memory elements is individually programmable to have different resistances.
13. The IC device of claim 11 , wherein
the plurality of source lines and the first and second word lines in each of the plurality of word line sets are elongated along a first axis, and
the plurality of bit lines and the first and second auxiliary conductive lines in each of the plurality of auxiliary conductive line sets are elongated along a second axis transverse to the first axis.
14. The IC device of claim 13 , wherein
in each of the plurality of memory cells and along the first axis,
the corresponding bit line is arranged between the corresponding first and second auxiliary conductive lines,
the first memory element is arranged between the third and fourth memory elements,
the fourth memory element is arranged between the first and second memory elements, and
the corresponding bit line and the corresponding first and second auxiliary conductive lines are arranged between first and second via structures at which the corresponding source line is correspondingly electrically coupled to the second memory element and the third memory element.
15. The IC device of claim 13 , wherein
the plurality of memory cells comprises first and second memory cells adjacent each other along the first axis, and
the IC device comprises an isolation structure between the first and second memory cells.
16. The IC device of claim 13 , wherein
the plurality of memory cells comprises first and second memory cells adjacent each other along the first axis,
the corresponding first and second word lines electrically coupled to the first memory cell are arranged over the first and second memory cells, and
the corresponding first and second word lines electrically coupled to the second memory cell are arranged under the first and second memory cells.
17. The IC device of claim 11 , wherein
the plurality of memory cells is arranged in a plurality of memory layers stacked one upon another.
18. The IC device of claim 17 , wherein
the plurality of memory layers comprises a plurality of stacks of memory elements arranged one over another, and
in each stack among the plurality of stacks,
each of the memory elements comprises a channel structure, and a memory film extending around the channel structure, and
a common gate structure extending around the memory films and the channel structures of all of the memory elements in said stack.
19. The IC device of claim 17 , wherein
the plurality of bit lines and the plurality of auxiliary conductive line sets are arranged in a stepwise structure having a plurality of steps corresponding to the plurality of memory layers.
20. A method, comprising:
in a read operation of a memory cell having a plurality of memory strings coupled in parallel between a bit line and a source line, wherein each of the plurality of memory strings comprises n memory elements coupled in series between the bit line and the source line and correspondingly coupled to n word lines, where n is an integer greater than 1, and wherein each memory element of the n memory elements of each of the memory strings is programmable to have different resistances,
applying a turn-ON voltage to the n word lines for turning ON each of the n memory elements of each of the memory strings of the memory cell, and
detecting a total resistance of the memory cell to detect data stored in the memory cell.