Integrated circuit device and methods
An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.
1 . An integrated circuit (IC) device, comprising:
a plurality of memory cells each comprising:
a first memory element which is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line,
a second memory element which is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor, the first memory element and the second memory element arranged in a first row along the first axis,
a third memory element which is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor, the first conductor electrically coupled to the second conductor, and
a fourth memory element which is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line, the third memory element and the fourth memory element arranged in a second row along the first axis, the first row spaced from the second row along a second axis transverse to the first axis.
2 . The IC device of claim 1 , wherein
in each of the plurality of memory cells,
each of the first through fourth memory elements is individually programmable to have different resistances.
3 . The IC device of claim 1 , further comprising:
a first word line along the first row, and electrically coupled to the first memory element and the second memory element; and
a second word line along the second row, and electrically coupled to the third memory element and the fourth memory element.
4 . The IC device of claim 1 , wherein
in each of the plurality of memory cells and along the first axis,
the bit line is physically arranged between the first auxiliary conductive line and the second auxiliary conductive line,
the first memory element is physically arranged between the third memory element and the fourth memory element, and
the fourth memory element is physically arranged between the first memory element and the second memory element.
5 . The IC device of claim 1 , wherein
in each of the plurality of memory cells and along the first axis,
the bit line, the first auxiliary conductive line and the second auxiliary conductive line are physically arranged between a first via structure and a second via structure at which a source line is electrically coupled to the first conductor and the second conductor.
6 . The IC device of claim 1 , wherein
the plurality of memory cells comprises a first memory cell and a second memory cell adjacent each other along the first axis, and
the IC device further comprises an isolation structure physically between the first memory cell and the second memory cell along the first axis.
7 . The IC device of claim 6 , wherein
the isolation structure is physically between the first conductor of the first memory cell and the second conductor of the second memory cell.
8 . The IC device of claim 7 , further comprising:
a source line electrically coupled to
the first conductor and the second conductor of the first memory cell, and
the first conductor and the second conductor of the second memory cell.
9 . The IC device of claim 1 , wherein
the plurality of memory cells comprises a first memory cell and a second memory cell adjacent each other along the first axis, and
the IC device further comprises:
at least one top word line physically arranged over the first memory cell and the second memory cell, and electrically coupled to the first memory cell without being electrically coupled to the second memory cell.
10 . The IC device of claim 9 , wherein
the at least one top word line comprises:
a first top word line along the first row, and electrically coupled to the first memory element and the second memory element of the first memory cell, and
a second top word line along the second row, and electrically coupled to the third memory element and the fourth memory element of the first memory cell.
11 . The IC device of claim 9 , wherein
the IC device further comprises:
at least one bottom word line physically arranged under the first memory cell and the second memory cell, and electrically coupled to the second memory cell without being electrically coupled to the first memory cell.
12 . The IC device of claim 11 , wherein
the at least one top word line comprises:
a first top word line along the first row, and electrically coupled to the first memory element and the second memory element of the first memory cell, and
a second top word line along the second row, and electrically coupled to the third memory element and the fourth memory element of the first memory cell, and
the at least one bottom word line comprises:
a first bottom word line along the first row, and electrically coupled to the first memory element and the second memory element of the second memory cell, and
a second bottom word line along the second row, and electrically coupled to the third memory element and the fourth memory element of the second memory cell.
13 . The IC device of claim 1 , wherein
the plurality of memory cells is arranged in a plurality of memory layers stacked one upon another.
14 . An integrated circuit (IC) device, comprising:
a substrate; and
a memory array layer over the substrate, the memory array layer comprising a plurality of memory cells each comprising a set of memory elements, wherein
the plurality of memory cells comprises a first memory cell, and a second memory cell adjacent the first memory cell along a first axis,
the set of memory elements of the first memory cell and the set of memory elements of the second memory cell are electrically coupled to
a same set of word lines,
a same source line, and
corresponding first and second bit lines, and
the IC device further comprises, in the memory array layer and along the first axis, an isolation structure between the first memory cell and the second memory cell.
15 . The IC device of claim 14 , wherein
the first memory cell comprises a first conductor coupled to the source line,
the second memory cell comprises a second conductor coupled to the source line, and
the isolation structure is physically between the first conductor and the second conductor along the first axis.
16 . A method, comprising:
patterning a multilayer structure comprising at least one memory array layer, to obtain
an opening between a first portion and a second portion of the multilayer structure, and
at least one channel extending across the opening from the first portion to the second portion, the at least one channel belonging to at least one active region layer in the at least one memory array layer;
depositing a memory film around the at least one channel;
depositing a conductive material in the opening; and
patterning the deposited conductive material to obtain at least one gate electrode around at least one channel.
17 . The method of claim 16 , wherein
the at least one memory array layer comprises a plurality of memory array layers stacked one over another.
18 . The method of claim 17 , further comprising:
patterning the multilayer structure to form a stepwise structure comprising a plurality of steps each containing source/drain contacts in a corresponding one of the plurality of memory array layers.
19 . The method of claim 17 , wherein
the at least one gate electrode comprises a plurality of gate electrodes,
the at least one channel comprises a plurality of channel stacks in each of which multiple channels, each belonging to a corresponding memory array layer among the plurality of memory array layers, are stacked over and spaced from each other, and
for each channel stack among the plurality of channel stacks,
the deposited memory film comprises multiple separate portions each extending around a corresponding one of the multiple channels in the channel stack, and
a corresponding gate electrode among the plurality of gate electrodes obtained by said patterning the deposited conductive material extends around the multiple separate portions of the memory film.
20 . The method of claim 16 , wherein the at least one gate electrode comprises a plurality of gate electrodes, the method further comprising:
depositing an insulating material between adjacent gate electrodes among the plurality of gate electrodes.