SRAM based memory structures and methods thereof
Technologies are generally described herein for static random access memory (SRAM) based memory structures and methods thereof such as multi-bit non-volatile static random-access memory (nvSRAM) with arrayed SRAM and NVM or SRAM buffered one time programmable (OTP) memories, RRAMs or other resistive RAMs.
1. A multi-bit non-volatile static random access memory (nvSRAM) device, comprising:
a static random access memory (SRAM) array having a plurality of SRAM cells arranged by rows of word lines and columns of bit lines;
a non-volatile memory (NVM) array having a plurality of NVM cells arranged in a column; and
one or more of switch devices coupled between one side of the SRAM array and the NVM array and configured to control connection between SRAM bit lines (BLs) and the NVM array, wherein another side of each of the SRAM columns is coupled to a reference circuit comprising a transistor device configured as an NVM cell with a source terminal coupled to an SRAM BL and a drain terminal coupled to a reference source line, and a capacitor coupled between the SRAM BL and a ground reference.
2. The multi-bit nvSRAM device of claim 1 , wherein at least a portion of control gates of the SRAM cells are coupled to a same SRAM word line (WL), and wherein one or more sources and one or more drains of at least some of the SRAM cells are coupled to the SRAM bit lines (BL).
3. The multi-bit nvSRAM device of claim 2 , wherein data of one row of SRAM cells are transferred to or from one of N rows of NVM cells connected to the one row of SRAM cells with N greater or equal to 1.
4. The multi-bit nvSRAM device of claim 1 , wherein the NVM cells are arranged in a single cell configuration.
5. The multi-bit nvSRAM device of claim 1 , wherein at least a portion of control gates of the NVM cells are coupled to a same NVM word line (WL), and wherein one or more sources and one or more drains of at least some of the NVM cells are coupled to the NVM bit line (BL) and a source line (SL).
6. The multi-bit nvSRAM device of claim 1 , wherein the one or more switch devices include a NMOS transistor or a PMOS transistor.
7. The multi-bit nvSRAM device of claim 1 , wherein the one or more switch devices are turned on to facilitate a data transfer between the SRAM cells and the NVM cells.
8. The multi-bit nvSRAM device of claim 1 , wherein the one or more switch devices are turned off to disconnect the SRAM BL from the NVM BL.
9. The multi-bit nvSRAM device of claim 1 , wherein at least one of the NVM cells includes a SONOS split gate cell, a floating gate cell, an eFlash cell, a pFlash cell, a 1T/1R resistive RAM, a resistive memory based cell, a phase change memory based cell, a ferroelectric RAM based cell, or a magnetic RAM based cell.
10. The multi-bit nvSRAM device of claim 1 , wherein SRAM bit-line loading is separated from NVM bit-line using the one or more switch devices such that a read/write speed of the multi-bit nvSRAM device is increased and a read/write current of the multi-bit nvSRAM device is reduced.
11. The multi-bit nvSRAM device of claim 1 , wherein each of the NVM cells comprises a switch device and a nonvolatile memory device with different memorized states.
12. The multi-bit nvSRAM device of claim 1 , wherein each of the NVM cells comprises a nonvolatile memory device with different memorized states.
13. The multi-bit nvSRAM device of claim 1 , wherein the one side of each SRAM BL is charged through the NVM column and the other side of each SRAM BL is charged through the reference circuit.