Integrated circuit device and methods

1. An integrated circuit (IC) device, comprising:

a substrate;

a memory array layer over the substrate, the memory array layer comprising a plurality of transistors;

first through fourth gate contacts arranged along a first axis, and coupled to underlying gates of the plurality of transistors;

first through fifth source/drain contacts in the memory array layer, extending along a second axis transverse to the first axis, and coupled to underlying source/drains of the plurality of transistors, wherein the gate contacts and the source/drain contacts are alternatingly arranged along the first axis;

a source line extending along the first axis, and coupled to the first and fifth source/drain contacts; and

first and second word lines extending along the first axis, the first word line coupled to the first and third gate contacts, the second word line coupled to the second and fourth gate contacts.

2. The IC device of claim 1 , further comprising:

a memory layer arranged on opposite sides of each of the first through fourth gate contacts.

3. The IC device of claim 2 , wherein

the memory array layer comprises an active region layer, and

for each of the plurality of transistors,

the active region layer comprises a channel, and a pair of source/drains connected by the channel, and

the memory layer extends around the channel.

4. The IC device of claim 3 , wherein, for each of the plurality of transistors,

in a cross-section along a plane perpendicular to the first axis, the memory layer extends around the channel for full 360 degrees.

5. The IC device of claim 3 , wherein, for each of the plurality of transistors,

the channel has a smaller dimension along the second axis than the pair of source/drains, and

the memory layer comprises:

a pair of end parts correspondingly adjacent to the pair of source/drains, and

a middle part connecting the pair of end parts, and having a smaller dimension along the second axis than the pair of end parts.

6. The IC device of claim 5 , wherein

each of the plurality of transistors further comprises a gate electrode extending around the middle part of the memory layer, without covering the pair of end parts as viewed along a third axis which is transverse to both the first axis and the second axis.

7. The IC device of claim 1 , wherein

each of the source/drain contacts extends continuously along the second axis over, and electrically coupled to, the underlying source/drains of multiple transistors among the plurality of transistors.

8. The IC device of claim 1 , further comprising:

a plurality of memory array layers including the memory array layer, and stacked one over another along a third axis which is transverse to both the first axis and the second axis.

9. The IC device of claim 8 , wherein

each of the plurality of memory array layers comprises an active region layer which includes a plurality of transistors,

each of the plurality of transistors comprises:

in the active region layer, a channel, and a pair of source/drains connected by the channel, and

a memory layer extends around the channel.

10. The IC device of claim 9 , further comprising:

a plurality of transistor stacks, wherein each of the plurality of transistor stacks includes stacked transistors each in a corresponding one of the plurality of memory array layers; and

a plurality of gate electrodes each coupling together gates of the stacked transistors in a corresponding one of the plurality of transistor stacks.

11. The IC device of claim 10 , wherein, for each transistor stack among the plurality of transistor stacks,

the memory layer comprises multiple separate portions each extending around the channel of a corresponding transistor in the transistor stack, and

the corresponding gate electrode extends around the multiple separate portions of the memory layer.

12. The IC device of claim 10 , further comprising:

a plurality of bottom word lines each

extending continuously along the first axis, and

underlying and coupled to a first set of gate electrodes among the plurality of gate electrodes.

13. The IC device of claim 12 , further comprising:

a plurality of top word lines each

extending continuously along the first axis, and

overlying and coupled to a second set of gate electrodes among the plurality of gate electrodes, the second set different from the first set.

14. The IC device of claim 8 , further comprising:

a stepwise structure comprising a plurality of steps each containing the source/drain contacts in a corresponding one of the plurality of memory array layers.

15. The IC device of claim 1 , wherein

the first through fourth gate contacts and the first through fifth source/drain contacts belong to a first memory cell,

the IC device further comprises:

a second memory cell having a same configuration as the first memory cell, and adjacent to the first memory cell along the first axis, and

an isolation structure between the first and second memory cells.

16. A method, comprising:

patterning a multilayer structure comprising at least one memory array layer, to obtain

an opening between a first portion and a second portion of the multilayer structure, and

a plurality of channels extending across the opening from the first portion to the second portion, the plurality of channels belonging to at least one active region layer in the at least one memory array layer;

depositing a memory film

over first and second walls of the opening correspondingly on the first and second portions of the multilayer structure, and

around each of the plurality of channels;

depositing a conductive material in the opening;

patterning the deposited conductive material to obtain a plurality of gate electrodes each individually around at least one corresponding channel among the plurality of channels; and

depositing an insulating material between adjacent gate electrodes among the plurality of gate electrodes.

17. The method of claim 16 , wherein

the at least one memory array layer comprises a plurality of memory array layers stacked one over another.

18. The method of claim 17 , further comprising:

patterning the multilayer structure to form a stepwise structure comprising a plurality of steps each containing source/drain contacts in a corresponding one of the plurality of memory array layers.

19. The method of claim 17 , wherein

the plurality of channels obtained by said patterning the multilayer structure includes a plurality of channel stacks in each of which multiple channels, each belonging to a corresponding memory array layer among the plurality of memory array layers, are stacked over and spaced from each other, and

for each channel stack among the plurality of channel stacks,

the deposited memory film comprises multiple separate portions each extending around a corresponding one of the multiple channels in the channel stack, and

a corresponding gate electrode among the plurality of gate electrodes obtained by said patterning the deposited conductive material extends around the multiple separate portions of the memory film.

20. A method, comprising:

in a memory cell having a plurality of memory strings coupled in parallel between a bit line and a source line, wherein each of the plurality of memory strings comprises n memory elements coupled in series between the bit line and the source line and correspondingly coupled to n word lines, where n is an integer greater than 1, and wherein each memory element of the n memory elements of each of the memory strings is programmable to have different resistances, a programming operation of a selected memory element of the memory cell comprising

applying a turn-ON voltage to, among the n word lines, a word line coupled to the selected memory element for turning ON the selected memory element, and

applying a programming voltage across the selected memory element to individually program the selected memory element to have one of the different resistances.