Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
1. A method, comprising:
forming a semiconductor on insulator (SOI) substrate having a compressively stressed buried oxide (BOX) structure between a surface semiconductor layer and a silicon substrate; and
subsequently defining device active regions in the surface semiconductor layer by etching trenches that penetrate through the surface semiconductor layer and the compressively stressed BOX structure and into the silicon substrate, whereby a boundary formed at a sidewall of at least one of the trenches allows the compressively stressed BOX structure to extend outwards and in so doing inducing a tensile strain in neighboring semiconductor lattices above and below the stressed BOX structure including into the surface semiconductor layer, the tensile strain induced into the surface semiconductor layer being non-uniform in its distribution.
2. The method of claim 1 , wherein the device active regions include channels of MOSFETs.
3. The method of claim 1 , wherein the trenches are positioned such that a lateral extent between two of the trenches is approximately 500 nm.
4. The method of claim 1 , wherein the surface semiconductor layer has a thickness of up to 50 nm.
5. The method of claim 1 , wherein the outward extension of the compressively stressed BOX structure induces a level of in-plane tensile stress of at least 200 megaPascal at a point over a span of the surface semiconductor layer between two of the trenches.
6. The method of claim 1 , wherein the surface semiconductor layer comprises silicon.
7. The method of claim 1 , wherein the surface semiconductor layer comprises germanium.
8. The method of claim 1 , wherein the surface semiconductor layer is a III-V compound semiconductor.
9. The method of claim 1 , wherein the surface semiconductor layer is a II-VI compound semiconductor.
10. The method of claim 1 , wherein the surface semiconductor layer is silicon carbide.
11. The method of claim 1 , wherein the compressively stressed BOX structure comprises a layer of SiGe positioned between a buried insulator layer and the silicon substrate, the SiGe layer being in a state of in-plane compressive stress.
12. The method of claim 11 , wherein the buried insulator layer comprises silicon dioxide.
13. The method of claim 1 , wherein the compressively stressed BOX structure comprises a layer of silicon nitride positioned between a buried insulator layer and the silicon substrate, the silicon nitride layer being in a state of in-plane compressive stress.
14. The method of claim 13 , wherein the buried insulator layer comprises silicon dioxide.
15. The method of claim 1 , wherein the compressively stressed BOX structure comprises a layer of silicon nitride, the layer of silicon nitride being in a state of in-plane compressive stress.
16. A method, comprising:
forming a semiconductor on insulator (SOI) substrate having a tensilely stressed buried oxide (BOX) structure between a surface semiconductor layer and a silicon substrate; and
subsequently defining device active regions in the surface semiconductor layer by etching trenches that penetrate through the surface semiconductor layer and the tensilely stressed BOX structure and into the silicon substrate, whereby a boundary formed at a sidewall of at least one of the trenches allows the tensilely stressed BOX structure to undergo edge relaxation and in so doing induce in-plane compressive strain into neighboring semiconductor lattices above and below the stressed BOX structure including into the surface semiconductor layer, the in-plane compressive strain induced into the surface semiconductor layer being non-uniform in its distribution.
17. The method of claim 16 , wherein the device active regions include channels of MOSFETs.
18. The method of claim 16 , wherein the trenches are positioned such that a lateral extent between two of the trenches is approximately 500 nm.
19. The method of claim 16 , wherein the surface semiconductor layer has a thickness of up to 50 nm.
20. The method of claim 16 , wherein the edge relaxation of the tensilely stressed BOX structure induces a magnitude of in-plane compressive stress of at least 200 megaPascal at a point over a span of the surface semiconductor layer between two of the trenches.
21. The method of claim 16 , wherein the surface semiconductor layer comprises silicon.
22. The method of claim 16 , wherein the surface semiconductor layer comprises germanium.
23. The method of claim 16 , wherein the surface semiconductor layer is a III-V compound semiconductor.
24. The method of claim 16 , wherein the surface semiconductor layer is a II-VI compound semiconductor.
25. The method of claim 16 , wherein the surface semiconductor layer is silicon carbide.
26. The method of claim 16 , wherein the tensilely stressed BOX structure comprises a layer of silicon nitride positioned between a buried insulator layer and the silicon substrate, the silicon nitride layer being in a state of in-plane tensile stress.
27. The method of claim 26 , wherein the buried insulator layer comprises silicon dioxide.
28. The method of claim 16 , wherein the tensilely stressed BOX structure comprises a layer of silicon nitride, the silicon nitride layer being in a state of in-plane tensile stress.