Semiconductor packages and method of manufacturing semiconductor packages

1. A semiconductor package, comprising:

a redistribution wiring layer having redistribution wirings;

a semiconductor chip on the redistribution wiring layer;

a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings; and

an antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another.

2. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thermal expansion coefficient, and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.

3. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient is within a range of ⅓ to ¼ of the first thermal expansion coefficient.

4. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.

5. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thickness, and the second antenna insulation layer has a second thickness greater than the first thickness.

6. The semiconductor package as claimed in claim 5 , wherein the first thickness of the first antenna insulation layer is in a range of 100 μm to 150 μm, and the second thickness of the second antenna insulation layer is in a range of 150 μm to 350 μm.

7. The semiconductor package as claimed in claim 1 , wherein the radiator pattern layer is electrically connected to the core connection wirings by a transmission line.

8. The semiconductor package as claimed in claim 7 , wherein the transmission line extends through a via hole in the ground pattern layer.

9. The semiconductor package as claimed in claim 1 , wherein the second antenna insulation layer includes a same material as the frame.

10. The semiconductor package as claimed in claim 1 , wherein the semiconductor chip includes a radio frequency integrated circuit (RFIC) for wireless communication.

11. A semiconductor package, comprising:

a frame having a cavity;

a semiconductor chip in the cavity, the semiconductor chip including chip pads;

a redistribution wiring layer on a lower surface of the frame, the redistribution wiring layer having redistribution wirings electrically connected to the chip pads of the semiconductor chip; and

an antenna structure on an upper surface of the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another,

wherein the first antenna insulation layer has a first thermal expansion coefficient, and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.

12. The semiconductor package as claimed in claim 11 , wherein the second thermal expansion coefficient is in a range of ⅓ to ¼ of the first thermal expansion coefficient.

13. The semiconductor package as claimed in claim 11 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.

14. The semiconductor package as claimed in claim 11 , wherein the first antenna insulation layer has a first thickness and the second antenna insulation layer has a second thickness greater than the first thickness.

15. The semiconductor package as claimed in claim 11 , wherein:

the frame includes core connection wirings, and

the radiator pattern layer is electrically connected to the core connection wirings by a transmission line, the transmission line extending through a via hole in the ground pattern layer.

16. A semiconductor package, comprising:

a semiconductor chip;

a frame surrounding the semiconductor chip, the frame having core connection wirings;

a redistribution wiring layer on a lower surface of the frame, the redistribution wiring layer having redistribution wirings electrically connected to chip pads of the semiconductor chip; and

an antenna structure on an upper surface of the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another,

wherein the radiator pattern layer is electrically connected to the redistribution wirings through the core connection wirings.

17. The semiconductor package as claimed in claim 16 , wherein the first antenna insulation layer has a first thermal expansion coefficient, and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.

18. The semiconductor package as claimed in claim 17 , wherein the second thermal expansion coefficient is within a range of ⅓ to ¼ of the first thermal expansion coefficient.

19. The semiconductor package as claimed in claim 17 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.

20. The semiconductor package as claimed in claim 16 , wherein the first antenna insulation layer has a first thickness and the second antenna insulation layer has a second thickness greater than the first thickness.