Die-to-die connectivity monitoring

1. An input/output (I/O) sensor for a multi-IC (Integrated Circuit) module, the I/O sensor comprising:

delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry comprising an adjustable delay-line configured to delay an input signal by a set time duration;

a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and

processing logic, configured to:

set the time duration of the adjustable delay-line,

based on the comparison signal, identify a margin measurement of the data signal, and

based on the margin measurement, determine a quality of connectivity between (a) the interconnected part of the IC of the multi-IC module and (b) an interconnected part of another IC of the multi-IC module.

2. The I/O sensor of claim 1 , wherein the processing logic is configured to:

for each of a plurality of time durations, set the adjustable delay-line to the respective time duration and determine whether the comparison signal for the respective time duration indicates a pass or a fail condition; and

identify a minimum time duration from the plurality of time durations for which the comparison signal indicates a fail condition.

3. The I/O sensor of claim 2 , wherein the processing logic is configured to repeat, for each of a plurality of measurement cycles, setting the adjustable delay-line to each of the plurality of time durations and identifying the minimum time duration and wherein the processing logic is further configured to determine one or more of: a lowest minimum time duration over the plurality of measurement cycles; a highest minimum time duration over the plurality of measurement cycles; and a sum of minimum time durations over the plurality of measurement cycles.

4. The I/O sensor of claim 1 , wherein the determination of the quality of connectivity comprises determining an interconnect quality parameter selected from the group consisting of: an eye pattern parameter; a micro-bump resistance parameter; a systematic effect parameter; and a parameter indicating a symmetry of differential signals.

5. The I/O sensor of claim 1 , wherein the margin measurement comprises one of: a data signal setup time to clock rising edge; a data signal setup time to clock falling edge; a data signal hold time to clock rising edge; and a data signal hold time to clock falling edge.

6. The I/O sensor of claim 1 , wherein the comparison circuit comprises an XOR gate and/or wherein the adjustable delay-line has a resolution of at least 1 ps and/or at least 16 configurations for the time duration.

7. The I/O sensor of claim 1 , wherein:

the data signal is provided as the input signal to the adjustable delay-line, and the data signal and the delayed data signal are sampled according to a clock signal, wherein the margin measurement relates to a data signal setup time.

8. The I/O sensor of claim 1 , wherein:

the data signal is sampled according to the clock signal, and the clock signal is provided as the input signal to the adjustable delay-line to provide a delayed clock signal, the delayed data signal being the data signal sampled according to the delayed clock signal, wherein the margin measurement relates to a data signal hold time.

9. The I/O sensor of claim, 1 wherein the delay circuitry further comprises:

a first state-element, configured to receive a first state-element input signal and to provide a first state-element output based on the first state-element input signal and a first clock input;

a second state-element, configured to receive a second state-element input signal and to provide a second state-element output based on the second state-element input signal and a second clock input; and

a multiplexing arrangement, configured selectively to apply one of:

the data signal as the input signal to the adjustable delay-line, an output of the adjustable delay-line being provided as the first state-element input signal, the data signal being provided as the second state-element input signal and a clock signal being provided as the first and second clock inputs; and

the clock signal as the input signal to the adjustable delay-line, an output of the adjustable delay-line being provided as the first clock input, the data signal being provided as the first and second state-element input signals and the clock signal being provided as the second clock input.

10. The I/O sensor of claim 9 , wherein the multiplexing arrangement is further configured to selectively apply as the clock signal:

a positive clock signal; or

a negative clock signal that is the positive clock signal inverted.

11. An input/output (I/O) block, comprising a plurality of I/O sensors, each I/O sensor being in accordance with claim 1 and being configured to receive a respective, different data signal from an interconnected part of the IC of the multi-IC module.

12. The I/O block of claim 11 , wherein the processing logic of each of the plurality of I/O sensors is located in a common control block.

13. The I/O block of claim 11 , wherein each I/O sensor is configured to receive a respective data signal from a different pin of the interconnected part of the IC of the multi-IC module, and, in parallel with the other sensors, identify a margin measurement for the respective pin.

14. An input/output (I/O) block for a multi-IC (Integrated Circuit) module, the I/O block comprising:

a receive buffer, configured to receive a voltage signal from an interconnected part of an IC of the multi-IC module and to provide a receive buffer output; and

an I/O sensor in accordance with claim 1 , wherein the receive buffer output is provided as the data signal input to the delay circuitry.

15. The I/O block of claim 14 , wherein the I/O sensor is further configured to receive a clock signal input which is a clock signal associated with the received voltage signal.

16. The I/O block of claim 14 , wherein the receive buffer is a first receive buffer and is configured to receive a first voltage signal from a first interconnected part of the semiconductor IC and provide a first receive buffer output, the I/O sensor being further configured to receive a clock signal input and wherein the I/O block further comprises:

a second receive buffer, configured to receive a second voltage signal from a second interconnected part of the semiconductor IC and to provide a second receive buffer output,

wherein the second receive buffer output, with a delay applied, is provided as the clock signal input.

17. The I/O block of claim 16 , wherein the I/O sensor is a first I/O sensor, the clock signal input being a first clock signal input, the I/O block further comprising:

a second I/O sensor, wherein the second receive buffer output is provided as the data signal input to the delay circuitry, the second I/O sensor being further configured to receive a second clock signal input,

wherein the first receive buffer output, with a delay applied, is provided as the second clock signal input.

18. The I/O block of claim 16 , further comprising:

a multiplexing arrangement, configured to selectively apply one of:

the first receive buffer output as the data signal input to the I/O sensor and the second receive buffer output with a delay applied as the clock signal input to the I/O sensor; and

the second receive buffer output as the data signal input to the I/O sensor and the first receive buffer output with a delay applied as the clock signal input to the I/O sensor.

19. The I/O block of claim 17 , wherein the first and second interconnected parts of the semiconductor IC form a differential channel.

20. The I/O block of claim 14 , wherein the I/O block is located on the IC of the multi-IC module and is configured to interface with an external processor for storing of the identified margin measurement and/or determining the interconnect quality parameter.

21. An input/output (I/O) monitoring system, comprising:

a plurality of I/O blocks, each I/O block being in accordance with claim 11 ; and

a common I/O controller configured to control said plurality of I/O blocks.