Die-to-die connectivity monitoring
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
1 . A multi-IC (Integrated Circuit) module comprising:
a first IC comprising a transmitter configured to transmit data signals; and
a second IC interconnected to said first IC over an interconnect lane, wherein said second IC comprises:
a receiver configured to receive the data signals, and
a sensor comprising:
an adjustable delay line configured to receive a clock signal associated with the data signals, and to gradually delay the clock signal by applying a plurality of different time durations to the clock signal,
a first state-element clocked by the gradually delayed clock signal and configured to sample the data signals according to the different time durations applied to the clock signal,
a second state-element clocked by the clock signal and configured to sample the data signals according to the clock signal,
a comparison circuit configured to compare an output of the first state-element with an output of the second state-element, and
processing logic configured to:
set said adjustable delay line to the plurality of time durations, and
determine reliability of connectivity between the first and second ICs, based at least on a minimal one of the different time durations for which said comparison circuit indicates a difference between the outputs of the first and second state-elements.
2 . The multi-IC module of claim 1 , wherein:
said adjustable delay line is further configured to receive the data signals and to gradually delay the data signals by applying a plurality of different time durations to the data signals; and
said sensor further comprises a multiplexing arrangement, configured to select between:
(a) said adjustable delay line receiving the clock signal so as to gradually delay the clock signal, said first state-element being clocked by the gradually delayed clock signal and sampling the data signals according to the different time durations applied to the clock signal, and said second state-element being clocked by the clock signal and sampling the data signals according to the clock signal, and
(b) said adjustable delay line receiving the data signals so as to gradually delay the data signals, said first state-element being clocked by the clock signal and sampling the delayed data signals according to the clock signal, and said second state-element being clocked by the clock signal and sampling the data signals according to the clock signal.
3 . The multi-IC module of claim 2 , wherein:
the clock signal is a positive clock signal; and
when said multiplexing arrangement selects (a), the determining of the reliability of connectivity comprises measuring a hold time of the data signals relative to a rising edge of the clock signal.
4 . The multi-IC module of claim 2 , wherein:
the clock signal is a negative clock signal; and
when said multiplexing arrangement selects (a), the determining of the reliability of connectivity comprises measuring a hold time of the data signals relative to a falling edge of the clock signal.
5 . The multi-IC module of claim 2 , wherein:
the clock signal is a positive clock signal; and
when said multiplexing arrangement selects (b), the determining of the reliability of connectivity comprises measuring a setup time of the data signals relative to a rising edge of the clock signal.
6 . The multi-IC module of claim 2 , wherein:
the clock signal is a negative clock signal; and
when said multiplexing arrangement selects (b), the determining of the reliability of connectivity comprises measuring a setup time of the data signals relative to a falling edge of the clock signal.
7 . The multi-IC module of claim 1 , wherein the sensor further comprises:
a further state-element having a data input and a data output, and being configured to be clocked by the clock signal; and
an OR gate comprising:
a first input coupled to the output of said comparison circuit,
a second input coupled to an output of said further state-element, and
an output configured to provide the data input to said further state-element,
such that, following said comparison circuit indicating a difference between the outputs of the first and second state-elements, the output of said further state-element remains at a logical high level until said further state-element is reset.
8 . The multi-IC module of claim 7 , wherein said second IC further comprises a controller, said controller comprising:
a logic and a memory, said logic being configured to store, in said memory, a value corresponding to the minimal one of the different time durations,
wherein said logic is further configured to perform the storing only if the minimal one of the different time durations is lower than a value already stored in said memory and associated with a previous comparison by the comparison circuit.
9 . The multi-IC module of claim 7 , wherein said sensor further comprises:
a synchronizer configured to reset said further state-element, said synchronizer comprising two serially-connected state-elements so as to avoid metastability.
10 . The multi-IC module of claim 1 , wherein the data signals are received by the receiver during mission mode of the multi-IC module.
11 . A non-transitory computer-readable storage medium having stored thereon a computer-readable encoding of a sensor for a multi-IC module, wherein the multi-IC module comprises: a first IC comprising a transmitter configured to transmit data signals, and a second IC interconnected to said first IC over an interconnect lane, wherein the sensor is comprised in the second IC, and wherein the sensor comprises:
an adjustable delay line configured to receive a clock signal associated with the data signals, and to gradually delay the clock signal by applying a plurality of different time durations to the clock signal;
a first state-element clocked by the gradually delayed clock signal and configured to sample the data signals according to the different time durations applied to the clock signal;
a second state-element clocked by the clock signal and configured to sample the data signals according to the clock signal;
a comparison circuit configured to compare an output of the first state-element with an output of the second state-element; and
processing logic configured to:
set said adjustable delay line to the plurality of time durations, and
determine reliability of connectivity between the first and second ICs, based at least on a minimal one of the different time durations for which said comparison circuit indicates a difference between the outputs of the first and second state-elements.
12 . The non-transitory computer-readable storage medium of claim 11 , wherein:
said adjustable delay line is further configured to receive the data signals and to gradually delay the data signals by applying a plurality of different time durations to the data signals; and
said sensor further comprises a multiplexing arrangement, configured to select between:
(a) said adjustable delay line receiving the clock signal so as to gradually delay the clock signal, said first state-element being clocked by the gradually delayed clock signal and sampling the data signals according to the different time durations applied to the clock signal, and said second state-element being clocked by the clock signal and sampling the data signals according to the clock signal, and
(b) said adjustable delay line receiving the data signals so as to gradually delay the data signals, said first state-element being clocked by the clock signal and sampling the delayed data signals according to the clock signal, and said second state-element being clocked by the clock signal and sampling the data signals according to the clock signal.
13 . The non-transitory computer-readable storage medium of claim 12 , wherein:
the clock signal is a positive clock signal; and
when said multiplexing arrangement selects (a), the determining of the reliability of connectivity comprises measuring a hold time of the data signals relative to a rising edge of the clock signal.
14 . The non-transitory computer-readable storage medium of claim 12 , wherein:
the clock signal is a negative clock signal; and
when said multiplexing arrangement selects (a), the determining of the reliability of connectivity comprises measuring a hold time of the data signals relative to a falling edge of the clock signal.
15 . The non-transitory computer-readable storage medium of claim 12 , wherein:
the clock signal is a positive clock signal; and
when said multiplexing arrangement selects (b), the determining of the reliability of connectivity comprises measuring a setup time of the data signals relative to a rising edge of the clock signal.
16 . The non-transitory computer-readable storage medium of claim 12 , wherein:
the clock signal is a negative clock signal; and
when said multiplexing arrangement selects (b), the determining of the reliability of connectivity comprises measuring a setup time of the data signals relative to a falling edge of the clock signal.
17 . The non-transitory computer-readable storage medium of claim 11 , wherein the sensor further comprises:
a further state-element having a data input and a data output, and being configured to be clocked by the clock signal; and
an OR gate comprising:
a first input coupled to the output of said comparison circuit,
a second input coupled to an output of said further state-element, and
an output configured to provide the data input to said further state-element,
such that, following said comparison circuit indicating a difference between the outputs of the first and second state-elements, the output of said further state-element remains at a logical high level until said further state-element is reset.
18 . The non-transitory computer-readable storage medium of claim 17 , having further stored thereon a computer-readable encoding of a controller for the second IC, the controller comprising:
a logic and a memory, said logic being configured to store, in said memory, a value corresponding to the minimal one of the different time durations,
wherein said logic is further configured to perform the storing only if the minimal one of the different time durations is lower than a value already stored in said memory and associated with a previous comparison by the comparison circuit.
19 . The non-transitory computer-readable storage medium of claim 17 , wherein said sensor further comprises:
a synchronizer configured to reset said further state-element, said synchronizer comprising two serially-connected state-elements so as to avoid metastability.
20 . The non-transitory computer-readable storage medium of claim 11 , wherein the data signals are received by the receiver during mission mode of the multi-IC module.