Closed-loop control of driver slew rate

1. An integrated circuit comprising:

an output circuit to output an output signal, the output circuit including a pre-driver circuit to receive a rising slew code and a falling slew code, wherein the pre-driver circuit includes a first pre-driver having a number of control nodes to receive the rising slew code, and a second pre-driver having a number of control nodes to receive the falling slew code;

a sensing circuit to measure a rising slew and a falling slew of the output signal;

a compare circuit to compare each of the rising slew and the falling slew with a target slew; and

an adjust circuit responsive to the compare circuit to adjust at least one of the rising slew code and the falling slew code.

2. The integrated of claim 1 , wherein the output circuit further includes a driver, the driver having a pullup device coupled to the first pre-driver and a pulldown device coupled to the second pre-driver.

3. An integrated circuit comprising:

an output circuit to output an output signal, the output circuit including a pre-driver circuit to receive a rising slew code and a falling slew code;

a sensing circuit to measure a rising slew and a falling slew of the output signal wherein the sensing circuit includes:

a first comparator to provide a first signal based on a comparison between the output signal and a first reference signal; and

a second comparator to provide a second signal based on the output signal and a second reference signal, wherein a delay between a first edge of the first signal and a first edge of the second signal represents one of the rising slew and falling slew of the output signal

a compare circuit to compare each of the rising slew and the falling slew with a target slew; and

an adjust circuit responsive to the compare circuit to adjust at least one of the rising slew code and the falling slew code.

4. An integrated circuit comprising:

an output circuit to output an output signal, the output circuit including a pre-driver circuit to receive a rising slew code and a falling slew code;

a sensing circuit to measure a rising slew and a falling slew of the output signal; a compare circuit to compare each of the rising slew and the falling slew with a target slew, wherein the compare circuit includes a first delay line to delay a first signal to produce a first delayed signal, a second line to delay a second signal to produce a second delayed signal, and a phase detector circuit to compare a phase relationship between the first delayed signal and the second delayed signal; and

an adjust circuit responsive to the compare circuit to adjust at least one of the rising slew code and the falling slew code.

5. The integrated circuit of claim 4 , wherein:

the first delay line is configured to apply a first delay to the first signal based on a first delay code, and

the second delay line is configured to apply a second delay to the second signal based on a second delay code.

6. The integrated circuit of claim 5 further comprising a delay code generator programmable to set the first delay code and the second delay code based on the target delay.

7. An integrated circuit comprising:

an output circuit to output an output signal, the output circuit including a pre-driver circuit to receive a rising slew code and a falling slew code;

a sensing circuit to measure a rising slew and a falling slew of the output signal;

a compare circuit to compare each of the rising slew and the falling slew with a target slew;

an adjust circuit responsive to the compare circuit to adjust at least one of the rising slew code and the falling slew code; and

a selector to select one of a measurement of the rising slew and a measurement of the falling slew of the output signal.

8. A method comprising:

setting a slew code for a signal path;

driving an output signal at an output node of the signal path; measuring the slew of the output signal to obtain a measured slew, wherein measuring the slew of the output signal includes producing an edge of a first signal based on a first signal level of an edge the output signal, and producing an edge of a second signal based on a second signal level of the edge of the output signal, wherein a time interval between the edge of the first signal and the edge of the second signal represents the measured slew of the output signal;

comparing the measured slew with a target slew, wherein comparing the measured slew with the target slew includes delaying the first signal by a first delay to produce a first delayed signal, delaying the second signal by a second delay to produce a second delayed signal, and comparing a phase relationship between the first delayed signal and the second delayed signal; and

modifying the slew code based on the comparison.

9. The method of claim 8 , wherein modifying the slew code includes:

increasing a value of the slew code based on a first condition of the phase relationship between the first delayed signal and the second delayed signal; and

decreasing the value of the slew code based on a second condition of the phase relationship between the first delayed signal and the second delayed signal.

10. The integrated circuit of claim 1 , wherein the compare circuit includes a delay line having a number of input nodes to receive delay codes representing the target slew.

11. The integrated circuit of claim 10 , wherein the adjust circuit includes:

a first state machine having input nodes coupled to the compare circuit and output nodes coupled to the control nodes of the first pre-driver; and

a second state machine having input nodes coupled to the compare circuit and output nodes coupled to the control nodes of the second pre-driver.

12. The integrated circuit of claim 3 , wherein the compare circuit includes a delay line having a number of input nodes to receive delay codes representing the target slew.

13. The integrated circuit of claim 12 , wherein the adjust circuit includes:

a first state machine having input nodes coupled to the compare circuit and output nodes coupled to the pre-driver circuit; and

a second state machine having input nodes coupled to the compare circuit and output nodes coupled to the pre-driver circuit.

14. The integrated circuit of claim 7 , wherein the compare circuit includes a delay line having a number of input nodes to receive delay codes representing the target slew.

15. The integrated circuit of claim 14 , wherein the adjust circuit includes:

a first state machine having input nodes coupled to the compare circuit and output nodes coupled to the pre-driver circuit; and

a second state machine having input nodes coupled to the compare circuit and output nodes coupled to the pre-driver circuit.

16. A system comprising:

a first integrated circuit including,

an output circuit to output an output signal, the output circuit including a pre-driver circuit to receive a rising slew code and a falling slew code, wherein the pre-driver circuit includes a first pre-driver having a number of control nodes to receive the rising slew code, and a second pre-driver having a number of control nodes to receive the falling slew code;

a sensing circuit to measure a rising slew and a falling slew of the output signal;

a compare circuit to compare each of the rising slew and the falling slew with a target slew; and

an adjust circuit responsive to the compare circuit to adjust at least one of the rising slew code and the falling slew code; and

a second integrated circuit coupled to the first integrated circuit, wherein one of the first and second integrated circuit includes a random access memory device.

17. The system of claim 16 , wherein the output circuit further includes a driver, the driver having a pullup device coupled to the first pre-driver and a pulldown device coupled to the second pre-driver.

18. The system of claim 16 , wherein the compare circuit includes a delay line having a number of input nodes to receive delay codes representing the target slew.

19. The system of claim 18 , wherein the adjust circuit includes:

a first state machine having input nodes coupled to the compare circuit and output nodes coupled to the control nodes of the first pre-driver; and

a second state machine having input nodes coupled to the compare circuit and output nodes coupled to the control nodes of the second pre-driver.