IC with larger and smaller width contacts
An integrated circuit (IC) includes a substrate having a semiconductor surface layer, at least one capacitor above the semiconductor surface layer including a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric, functional circuitry in the semiconductor surface layer includes a core region having transistors configured together with the capacitor for realizing at least one circuit function. Electrically conductive metal filled contacts are through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reach the top capacitor plate, and second filled contact hole having a second depth and a second width that reach the core region. The second depth is deeper than the first depth, and the first width is at least ten (10) % larger than the second width.
1. A method of fabricating an integrated circuit (IC), comprising:
forming a dielectric layer over a capacitor that is over a semiconductor surface layer of a substrate, wherein the capacitor has a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric;
forming a patterned layer over the dielectric layer, the patterned layer having a first opening of a first width and second and third openings of a second width, wherein the semiconductor surface layer has functional circuitry for realizing at least one circuit function comprising a core region having a plurality of transistors configured together with at least the capacitor, and wherein the first width is at least ten (10) % larger than the second width;
using the patterned layer, etching a first contact hole in the dielectric layer at the first opening and second and third contact holes in the dielectric layer at the respective second and third openings, wherein the first contact hole extends a first depth to the top plate, the second contact hole extends a second depth to the core region, and the third contact hole extends to the bottom plate, wherein the second depth is deeper than the first depth, and
filling the first, second and third contact holes with an electrically conductive fill metal to form a first filled contact, a second filled contact and a third filled contact.
2. The method of claim 1 , wherein the top plate comprises TiN, Ti, or TaN.
3. The method of claim 1 , wherein the functional circuitry comprises a Complementary Metal-Oxide Semiconductor (CMOS) transistor.
4. The method of claim 1 , wherein the bottom plate comprises doped polysilicon.
5. The method of claim 4 , wherein the bottom plate comprises a silicide on the doped polysilicon.
6. The method of claim 1 , wherein the first width is at least (≥) 20% larger than the second width.
7. The method of claim 1 , wherein the capacitor dielectric comprises a dielectric stack comprising a silicon oxide layer and a silicon nitride or a silicon oxynitride layer.
8. The method of claim 1 , further comprising after the filling removing overburden regions of the electrically conductive fill metal using CMP.
9. An integrated circuit (IC), comprising:
a substrate having a semiconductor surface layer;
at least one capacitor above the semiconductor surface layer comprising a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric;
functional circuitry in the semiconductor surface layer comprising a core region having a plurality of transistors configured together with the capacitor for realizing at least one circuit function, and
electrically conductive metal filled contacts through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reaches the top capacitor plate, a second filled contact hole having a second depth and a second width that reaches the core region, and a third filled contact hole that contacts the bottom plate having the second width,
wherein the second depth is deeper than the first depth, and wherein the first width is at least ten (10) % larger than the second width.
10. The IC of claim 9 , wherein the top plate comprises TiN, Ti, or TaN.
11. The IC of claim 9 , wherein the functional circuitry comprises a Complementary Metal-Oxide Semiconductor (CMOS) transistor.
12. The IC of claim 9 , wherein the bottom plate comprises doped polysilicon.
13. The IC of claim 12 , wherein the bottom plate comprises a silicide layer on the doped polysilicon.
14. The IC of claim 9 , wherein the first width is at least (≥) 20% larger than the second width.
15. The IC of claim 9 , wherein a thickness of the capacitor dielectric is 20 nm to 200 nm.
16. The IC of claim 9 , wherein the capacitor dielectric comprises a dielectric stack comprising a silicon oxide layer and a silicon nitride or a silicon oxynitride layer.
17. The IC of claim 9 , wherein the capacitor is formed on field oxide that is on the semiconductor surface layer.
18. The IC of claim 17 , wherein the field oxide comprises shallow trench isolation (STI).