IP Library › Granted Patent US 12,216,976
Granted Patent B2
US 12,216,976 · App. 17/485,168 · Granted Feb 4, 2025

Efficient integrated circuit simulation and testing

Inventors: Evelyn Landman (Haifa, IL); Yair Talker (Binyamina, IL); Eyal Fayneh (Givatayim, IL); Yahel David (Kibbutz Gazit, IL); Shai Cohen (Haifa, IL); Inbar Weintrob (Givat-Ada, IL)
Assignee: PROTEANTECS LTD.
G06F30/3312G06F2111/08G06F2119/06G06F2119/22
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Quick Facts
Patent No.
US 12,216,976
App. No.
17/485,168
Granted
Feb 4, 2025
Kind
B2
Abstract

A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

Claims (55)

1. A method comprising using at least one hardware processor for:

running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types;

based on results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations;

receiving an IC design embodied as a digital file;

correlating the received IC design with the library; and

based on said correlating, predicting at least one of:

a frequency distribution, or

a power distribution,

of ICs manufactured according to the IC design.

2. The method according to claim 1 , wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects.

3. The method according to claim 1 , wherein said correlating comprises retrieving, from the library, behavioral values that pertain to cell types that exist in the IC design.

4. The method according to claim 3 , further comprising:

running an electronic circuit simulation of the IC design to identify possible IC process variations, based on the behavioral values retrieved from the library.

5. The method according to claim 1 , further comprising, based on said correlating:

predicting critical paths that limit a frequency of the ICs manufactured according to the IC design,

wherein said predicting of at least one of the frequency distribution and the power distribution is based on said critical paths prediction.

6. The method according to claim 5 , further comprising:

identifying a ranked list of the critical paths, out of paths in the IC design, based on the behavioral values retrieved from the library.

7. The method according to claim 1 , wherein the behavioral values are values that affect at least one operational parameter of an IC manufactured based on the IC design, wherein the at least one operational parameter is selected from the group consisting of: voltage, current, delay, and frequency.

8. The method according to claim 1 , wherein the library of IC cell types comprises an operational model for each IC cell type, the operational model comprising aging degradation data and a Static Timing Analysis (STA) model.

9. The method according to claim 1 , further comprising:

receiving Post-Si data, derived from ICs manufactured according to the IC design; and

adjusting the library based on the received Post-Si data.

10. The method according to claim 9 , further comprising:

receiving on-chip measurements from ICs manufactured according to the IC design, wherein the on-chip measurements are derived from one or more on-chip sensors of each of the manufactured ICs, wherein the one or more on-chip sensors comprise at least one of: a timing-margin sensor, a delay sensor, a leakage sensor, a voltage sensor, and a thermal sensor; and

using the on-chip measurements as an input to an estimator, the Post-Si data being provided as an output from the estimator.

11. The method according to claim 1 , further comprising:

(a) manufacturing ICs according to the IC design; and setting one or more operational parameters of the manufactured ICs based on the stored library; or

(b) setting one or more manufacturing parameters based on the stored library, and manufacturing ICs according to the IC design and the manufacturing parameters.

12. A system comprising:

(a) at least one hardware processor; and

(b) a non-transitory computer-readable storage medium having program code embodied therewith, the program code executable by said at least one hardware processor to:

run a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types,

based on results of the Monte Carlo simulation, create a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations;

receive an IC design embodied as a digital file;

correlate the received IC design with the library, and

based on said correlating, predict at least one of:

a frequency distribution, or

a power distribution,

of ICs manufactured according to the IC design.

13. The system according to claim 12 , wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects.

14. The system according to claim 12 , wherein said correlating comprises retrieving, from the library, behavioral values that pertain to cell types that exist in the IC design.

15. The system according to claim 14 , wherein the program code is further executable to:

run an electronic circuit simulation of the IC design to identify possible IC process variations, based on the behavioral values retrieved from the library.

16. The system according to claim 12 , wherein the program code is further executable, based on said correlating, to:

predict critical paths that limit a frequency of the ICs manufactured according to the IC design,

wherein said predicting of at least one of the frequency distribution and the power distribution is based on said critical paths prediction.

17. The system according to claim 16 , wherein the program code is further executable to:

identify a ranked list of the critical paths, out of paths in the IC design, based on the behavioral values retrieved from the library.

18. The system according to claim 12 , wherein the behavioral values are values that affect at least one operational parameter of an IC manufactured based on the IC design, wherein the at least one operational parameter is selected from the group consisting of: voltage, current, delay, and frequency.

19. The system according to claim 12 , wherein the library of IC cell types comprises an operational model for each IC cell type, the operational model comprising aging degradation data and a Static Timing Analysis (STA) model.

20. The system according to claim 12 , wherein the program code is further executable to:

receive on-chip measurements from ICs manufactured according to the IC design, wherein the on-chip measurements are derived from one or more on-chip sensors of each of the manufactured ICs, wherein the one or more on-chip sensors comprise at least one of: a timing-margin sensor, a delay sensor, a leakage sensor, a voltage sensor, and a thermal sensor; and

operate an estimator to output Post-Si data based on the on-chip measurements; and

adjust the library based on the Post-Si data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2021
From: LANDMAN, EVELYN; TALKER, YAIR; FAYNH, EYAL; DAVID, YAHEL; COHEN, SHAI; WEINTROB, INBAR
To: PROTEANTECS LTD.
Reel/Frame 057599/0586 →
Continuity (3)
Continuation 17254468
Provisional Application 62686744 · Jun 19, 2018
Related Publication 20220012395A1 · Jan 13, 2022
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