Digital system for the detection of variations in operating conditions of an integrated circuit
A system for detecting tamper events in a digital circuit by having a Critical Path Replica (CPR) circuit operable in parallel with the circuit being monitored, and adjusted to generate a timing violation if the operating parameters of the circuit change to be outside the normal operating parameters. The critical path replica circuit is adjusted to generate a timing violation before the actual circuit being monitored fails due to the changed operating parameters.
1. A tamper detection system comprising:
a launch clock replica circuit receiving a clock signal at an input and generating a launch clock signal at an output;
a waveform generator register having a latch input connected to said output of said launch clock replica, an input and an output;
an inverter having an input connected to said output of said waveform generator and an output connected to said input of said waveform generator;
a critical path replica circuit having an input connected to said output of said waveform generator and an output, said critical path replica circuit having a delay corresponding to a delay of a critical path of a circuit to be protected;
a variable delay circuit having an input connected to said output of said critical path replica circuit and an output, said variable delay circuit having a specified delay;
a capture clock replica circuit receiving a clock signal at an input and generating a capture clock signal at an output;
a register having a latch input connected to said output of said capture clock replica circuit, an input connected to said output of said variable delay circuit and an output;
an exclusive NOR gate having a first input connected to said output of said waveform generator, a second input connected to said output of said register and an output;
a counter having an enable input connected to said output of said exclusive NOR gate, a clock input connected to said output of said capture clock replica circuit and an overflow output, said counter counting clock signals at said clock input when said exclusive NOR indicates said output of said waveform generator does not match said output of said register and generating an overflow signal at said overflow output indicating tampering upon overflow.
2. The tamper detection system of claim 1 , wherein:
said critical path replica circuit is disposed physically close to said critical path of said circuit to be protected.
3. The tamper detection system of claim 1 , wherein:
said delay of said variable delay circuit is selected whereby said counter indicates overflow before said critical path of said circuit to be protected fails.
4. The tamper detection system of claim 1 , wherein:
said counter includes a reset input and is periodically reset.
5. The tamper detection system of claim 1 , wherein:
said counter includes a count input for receiving a predetermined count.
6. A tamper detection system comprising:
a launch clock replica circuit receiving a clock signal at an input and generating a launch clock signal at an output;
a waveform generator register having a latch input connected to said output of said launch clock replica circuit, an input and an output;
an inverter having an input connected to said output of said waveform generator and an output connected to said input of said waveform generator;
a critical path replica circuit having an input connected to said output of said waveform generator and an output, said critical path replica circuit having a delay corresponding to a delay of a critical path of a circuit to be protected;
a capture clock replica circuit receiving a clock signal at an input and generating a capture clock signal at an output;
a variable delay circuit having an input connected to said output of said capture clock replica circuit and an output, said variable delay circuit having a specified delay;
a register having a latch input connected to said output of said variable delay circuit, an input connected to said output of said critical path replica circuit and an output;
an exclusive NOR gate having a first input connected to said output of said waveform generator, a second input connected to said output of said register and an output;
a counter having an enable input connected to said output of said exclusive NOR gate, a clock input connected to said output of said capture clock replica circuit and an overflow output, said counter counting clock signals at said clock input when said exclusive NOR indicates said output of said waveform generator does not match said output of said register and generating an overflow signal at said overflow output indicating tampering upon overflow.
7. The tamper detection system of claim 6 , wherein:
said critical path replica circuit is disposed physically close to said critical path of said circuit to be protected.
8. The tamper detection system of claim 6 , wherein:
said delay of said variable delay circuit is selected whereby said counter indicates overflow before said critical path of said circuit to be protected fails.
9. The tamper detection system of claim 6 , wherein:
said counter includes a reset input and is periodically reset.
10. The tamper detection system of claim 6 , wherein:
said counter includes a count input for receiving a predetermined count.