Methods, systems and apparatus for dynamic temperature aware functional safety
The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.
1. A processing device comprising:
a die having integrated thereon:
a plurality of ring oscillators configured to have a temperature-varying frequency at an output; and
a storage device configured to store data indicating a relationship between temperature and an output frequency of each of the plurality of ring oscillators; and
circuitry configured to:
determine a temperature of a first region corresponding to a current output frequency of a first ring oscillator of the plurality of ring oscillators, the first region comprising a Central Processing Unit (CPU), and the temperature of the first region being determined using the stored data indicating the relationship between temperature and output frequency for the first ring oscillator;
determine a temperature of a second region corresponding to a current output frequency of a second ring oscillator of the plurality of ring oscillators, the second region comprising a graphics processing unit (GPU), and the temperature of the second region being determined using the stored data indicating the relationship between temperature and output frequency for the second ring oscillator; and
provide a temperature measurement indicative of the temperature of the first region and the temperature of the second region.
2. The processing device of claim 1 , further comprising:
a controller configured to trigger a temperature reduction action based on the temperature measurement.
3. The processing device of claim 2 , wherein the temperature reduction action includes hardware throttling.
4. The processing device of claim 2 , wherein the temperature reduction action includes triggering a hardware thermal shutdown.
5. The processing device of claim 1 , wherein the processing device is included in a System-on-Chip (SoC).
6. The processing device of claim 1 , wherein each of the plurality of ring oscillators is calibrated before use.
7. A system-on-a-chip (SoC) comprising:
a die having integrated thereon:
a Central Processing Unit (CPU) at a first region of the SoC;
a first ring oscillator configured to have a temperature-varying frequency at an output, the first ring oscillator positioned at the first region of the SoC;
a storage device configured to store data indicating a relationship between temperature and an output frequency of the first ring oscillator; and
a temperature sensor configured to:
determine a temperature of the first region corresponding to a current output frequency of the first ring oscillator, the temperature of the first region being determined using the stored data indicating the relationship between temperature and output frequency for the first ring oscillator; and
provide a first temperature measurement indicative of the temperature of the first region.
8. The SoC of claim 7 , further comprising:
a graphics processing unit (GPU) at a second region of the SoC; and
a second ring oscillator configured to have a temperature-varying frequency at an output, the second ring oscillator positioned at the second region of the SoC;
wherein the storage device is configured to store data indicating a relationship between temperature and an output frequency of the second ring oscillator; and
wherein the temperature sensor is configured to determine a temperature of the second region corresponding to a current output frequency of the second ring oscillator, and provide second temperature measurement indicative of the temperature of the second region, the temperature of the second region being determined using the stored data indicating the relationship between temperature and output frequency for the second ring oscillator.
9. The SoC of claim 8 , further comprising a controller configured to trigger a temperature reduction action based on at least one of the first temperature measurement and the second temperature measurement.
10. The SoC of claim 9 , wherein the temperature reduction action includes hardware throttling.
11. The SoC of claim 9 , wherein the temperature reduction action includes triggering a hardware thermal shutdown.
12. The SoC of claim 7 , further comprising a high-speed input/output (I/O) interface.
13. The SoC of claim 7 , further comprising a camera interface.
14. At least one non-transitory machine-readable medium comprising instructions that, when executed by computing hardware, including a processor coupled to a memory circuitry and to a plurality of ring oscillators, cause the computing hardware to cause a System-on-Chip (SoC) to:
obtain stored data, from a storage device of the SoC, the stored data indicating a relationship between temperature and an output frequency of each of the plurality of ring oscillators;
determine a temperature of a first region corresponding to a current output frequency of a first ring oscillator of the plurality of ring oscillators, the first region comprising a Central Processing Unit (CPU), and the temperature of the first region being determined using the stored data indicating the relationship between temperature and output frequency for the first ring oscillator;
determine a temperature of a second region corresponding to a current output frequency of a second ring oscillator of the plurality of ring oscillators, the second region comprising a graphics processing unit (GPU), and the temperature of the second region being determined using the stored data indicating the relationship between temperature and output frequency for the second ring oscillator; and
provide a temperature measurement indicative of the temperature of the first region and the temperature of the second region.
15. The non-transitory machine-readable medium of claim 14 , wherein the instructions further cause the SoC to:
trigger a temperature reduction action based on the temperature measurement.
16. The non-transitory machine-readable medium of claim 15 , wherein the temperature reduction action includes hardware throttling.
17. The non-transitory machine-readable medium of claim 15 , wherein the temperature reduction action includes triggering a hardware thermal shutdown.
18. The processing device of claim 2 , wherein the temperature reduction action includes hardware throttling followed by a hardware thermal shutdown.
19. The SoC of claim 9 , wherein the temperature reduction action includes hardware throttling followed by a hardware thermal shutdown.
20. The SoC of claim 19 , further comprising:
a high-speed input/output (I/O) interface; and
a camera interface;
wherein the first ring oscillator and the second ring oscillator are calibrated before use.
21. The non-transitory machine-readable medium of claim 15 , wherein the temperature reduction action includes hardware throttling followed by a hardware thermal shutdown.
22. A system-on-a-chip (SoC) comprising:
a die having integrated thereon:
at least one of a high-speed input/output (I/O) interface or a camera interface;
a Central Processing Unit (CPU) at a first region of the SoC;
a first ring oscillator configured to have a temperature-varying frequency at an output, the first ring oscillator positioned at the first region of the SoC;
a Graphics Processing Unit (GPU) at a second region of the die;
a second ring oscillator configured to have a temperature-varying frequency at an output, the second ring oscillator positioned at the second region of the SoC;
a storage device configured to store data indicating a relationship between temperature and an output frequency of the first ring oscillator and the second ring oscillator;
a temperature sensor configured to:
determine a temperature of the first region corresponding to a current output frequency of the first ring oscillator, the first region comprising a Central Processing Unit (CPU), and the temperature of the first region being determined using the stored data indicating the relationship between temperature and output frequency for the first ring oscillator;
provide a first temperature measurement indicative of the temperature of the first region;
determine a temperature of the second region corresponding to a current output frequency of the second ring oscillator, the temperature of the second region being determined using the stored data indicating the relationship between temperature and output frequency for the second ring oscillator; and
provide a second temperature measurement indicative of the temperature of the second region; and
a controller configured to trigger a temperature reduction action based on at least one of the first temperature measurement and the second temperature measurement, wherein the temperature reduction action includes at least one of hardware throttling or a hardware thermal shutdown;
wherein the first ring oscillator and the second ring oscillator are calibrated before use.