Granted Patent B2

US 12,241,933 · App. 18/014,642 · Granted Mar 4, 2025

Inventors: Evelyn Landman (Haifa, IL); Eyal Fayneh (Givatayim, IL); Shai Cohen (Haifa, IL); Alex Khazin (Nesher, IL)

Assignee: PROTEANTECS LTD.

G01R31/318594G01R31/3016G01R31/318536H03K5/13

Abstract

Claims (43)

1. A method for testing a semiconductor integrated circuit (IC), the method comprising:

scanning test patterns into internal circuits of the semiconductor IC, the internal circuits of the semiconductor IC comprising a margin measurement sensor;

measuring a margin, using the margin measurement sensor, the margin being measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time,

wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time; and

scanning out an output of the margin measurement sensor.

2. The method of claim 1 , wherein the step of measuring comprises:

receiving, at a signal path combiner, a plurality of signal paths of the semiconductor IC; and

combining the received plurality of signal paths of the semiconductor IC to provide the test signal path.

3. The method of claim 1 , wherein the step of measuring the margin comprises identifying a delay time threshold based on multiple comparisons between the test signal path of the semiconductor IC and the delayed signal path for different delay times.

4. The method of claim 1 , wherein the method constitutes a structural test of the semiconductor IC, and wherein the margin measurement sensor comprises a data register forming part of a scan chain of the structural test, the method further comprising:

configuring the structural test by resetting the data register;

storing the measured characteristic of the delay in the data register; and

wherein the scanning out comprises scanning out the measured characteristic of a delay from the data register.

5. The method of claim 4 , wherein:

the data register is a first data register at the output of the margin measurement sensor, and the first data register is reset to configure the structural test by scanning in a reset pattern; or

the data register is a second data register that receives the measured characteristic of a delay from a first data register at the output of the margin measurement sensor, and the second data register is reset to configure the structural test by an output of the first data register.

6. The method of claim 1 , wherein the test patterns are generated using Automatic Test Pattern Generation (ATPG), and wherein the scanning out is performed using an ATPG shift mode.

7. The method of claim 1 , wherein the characteristic of a comparison comprises one or more of: a pass or fail condition; a delay threshold comparison result; a delay indication; and or a worst case delay indication.

8. The method of claim 1 , wherein the scanning of test patterns into the internal circuits of the semiconductor IC is controlled by a scan clock having a first frequency; and wherein an operation of the semiconductor IC, during which the measuring of the margin is performed, is controlled by a capture clock having a second frequency that is higher than the first frequency.

9. The method of claim 1 , further comprising operating in a characterization mode, in which:

the measuring of the margin comprises determining a minimum margin associated with one or more signal paths coupled to the margin measurement sensor for each of a plurality of structural test patterns at each of an Automatic Test Equipment and an Evaluation Board;

the determined minimum margin for each of the Automatic Test Equipment and the Evaluation Board is compared; and

performance of Automatic Test Equipment and the Evaluation Board is correlated.

10. The method of claim 1 , further comprising operating in High Volume Manufacturing (HVM) mode, by setting the variable delay time for the margin measurement sensor to a threshold value and classifying the IC based the measured margin using the threshold value.

11. A tester device configured to test a semiconductor integrated circuit (IC) by:

scanning test patterns from the tester device into a margin measurement sensor forming part of internal circuits of the semiconductor IC; and

scanning out an output of the margin measurement sensor from the semiconductor IC to the tester device, to receive at the tester device one or more margin measurements performed by the margin measurement sensor, each margin being measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path of the semiconductor IC, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time, wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time.

12. The tester device of claim 11 , wherein the characteristic of the comparison comprises one or more of: a pass or fail condition; a delay threshold comparison result; a delay indication; or a worst case delay indication.

13. The tester device of claim 11 , wherein each of the one or more margin measurements is performed by:

receiving, at a signal path combiner of the semiconductor IC, a plurality of signal paths of the semiconductor IC; and

combining the received plurality of signal paths of the semiconductor IC to provide the test signal path.

14. The tester device of claim 11 , wherein each of the one or more margin measurements is performed by identifying a delay time threshold based on multiple comparisons between the test signal path of the semiconductor IC and the delayed signal path for different delay times.

15. A semiconductor integrated circuit (IC), comprising:

structural test circuitry configured to receive test patterns and to run one or more structural tests on functional circuitry of the semiconductor IC; and

a margin measurement sensor configured to measure a margin, the margin comprising a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time, wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time.

16. The semiconductor IC of claim 15 , wherein the characteristic of the comparison comprises one or more of: a pass or fail condition, a delay threshold comparison result, a delay indication, or a worst case delay indication.

17. The semiconductor IC of claim 15 , wherein the measuring of the margin comprises identifying a delay time threshold based on multiple comparisons between the test signal path of the semiconductor IC and the delayed signal path for different delay times.

18. The semiconductor IC of claim 15 , wherein the margin measurement sensor comprises a data register forming part of a scan chain of the one or more structural tests, and wherein the one or more structural tests comprise:

configuring the respective structural test by resetting the data register;

storing the measured characteristic of the delay in the data register; and

scanning out the measured characteristic of the delay from the data register.

19. The semiconductor IC of claim 18 , wherein the data register is a first data register at the output of the margin measurement sensor, and the first data register is reset to configure the structural test by scanning in a reset pattern.

20. The semiconductor IC of claim 18 , wherein the data register is a second data register that receives the measured characteristic of the delay from a first data register at the output of the margin measurement sensor, and the second data register is reset to configure the structural test by an output of the first data register.

Assignments (1)

Continuity (2)

References Cited (294)

Cited By (1)

US 12,535,521