Structure for time based driver output transition (slew) rate compensation
View Patent ↗A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases (voltage-time relationships) of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.
1. A method in a computer-aided design system for generating a functional design model of a structure for time based driver output transition rate compensation, the method comprising:
generating, by a processor, a functional representation of a driver circuit having an input signal and an output signal, the driver circuit structured and arranged to control the slew rate of the output signal;
generating a functional representation of a delay circuit coupled to the output signal of the driver circuit, the delay circuit having a delay proportional to a desired target slew rate of the output signal;
generating a functional representation of a first comparator for detecting when the output signal rises through a specified level;
generating a functional representation of a second comparator for detecting when the output signal falls through a second specified level; and
generating a functional representation of a phase detector directly coupled to outputs of the first and second comparators and directly coupled to an output of the delay circuit, for aligning the phases (voltage-time relationships) of the comparator outputs with the phases of delayed comparator outputs by adjusting the slew rate of the output signal.
2. The method of claim 1 , wherein the functional design model comprises a netlist.
3. The method of claim 1 , wherein the functional design model resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The method of claim 1 , wherein the functional design model resides in a programmable gate array.
5. The method of claim 1 , further comprising a current limited inverter scheme comprising two current sources, for adjusting the slew rate of the output signal by controlling current through a prior stage.
6. The method of claim 5 , wherein the driver circuit compensates the slew rate of the output signal based on an error signal proportional to a difference between a measured driver output transition time and a time reference for a target driver output transition time by adjusting the measured transition time to the time reference, whereby the measured transition time corresponds to a driver output transition time of the prior stage.
7. The method of claim 1 , wherein one of the outputs of the first and second comparators is delayed by the delay circuit to provide an edge triggered digital error signal.
8. The method of claim 7 , further comprising at least one charge pump coupled to receive the edge triggered digital error signal, wherein the at least one charge pump generates bias signals for the driver circuit to control the slew rate of the output signal.
9. The method of claim 1 , wherein the phase detector is directly coupled to inverted outputs of the first and second comparators.
10. The method of claim 9 , wherein the phase detector is directly coupled to an inverse of the input signal and directly coupled to a buffered version of the input signal.
11. The method of claim 10 , wherein the phase detector comprises:
a first latch directly coupled to an output of the first comparator, directly coupled to the output of the delay circuit, and directly coupled to an inverted output of the first comparator; and
a second latch directly coupled to an output of the second comparator, directly coupled to the output of the delay circuit, and directly coupled to an inverted output of the second comparator.
12. The method of claim 11 , wherein the phase detector further comprises:
a first NAND gate directly coupled to the output of the delay circuit and directly coupled to the inverse of the input signal; and
a second NAND gate directly coupled to the output of the delay circuit and directly coupled to the buffered version of the input signal.
13. A method in a computer-aided design system for generating a functional design model of a structure for time based driver output transition rate compensation, the method comprising:
generating, by a processor, a functional representation of a delay circuit connectable to an output signal of a driver circuit, the delay circuit being tunable to establish a time reference;
generating a functional representation of a device to measure the transition rate for the rising and falling edges of the output signal;
generating a functional representation of a device to compare the measured transition rate to the time reference;
generating a functional representation of a control device structured and arranged to control an output slew rate of the driver circuit; and
generating a functional representation of a current limited inverter scheme comprising two current sources, arranged to adjust the output slew rate by controlling current through a prior stage.
14. The method of claim 13 , further comprising at least one charge pump coupled to the device to compare the measured transition rate to the time reference, the charge pump being structured and arranged to generate bias signals.
15. The method of claim 14 , wherein the control device is coupled to the at least one charge pump that is structured and arranged to receive the bias signals.
16. The method of claim 13 , wherein the control device compensates the driver circuit based on an error signal proportional to a difference between the measured transition rate and the time reference by adjusting the measured transition rate to the time reference, whereby the measured transition rate corresponds to an output transition rate of the prior stage.
17. The method of claim 13 , wherein the functional design model comprises a netlist.
18. The method of claim 13 , wherein the functional design model resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
19. The method of claim 13 , wherein the functional design model resides in a programmable gate array.
20. A method in a computer-aided design system for generating a functional design model of a structure for time based driver output transition rate compensation, the method comprising:
generating, by a processor, a functional representation of a driver circuit having an input signal and an output signal, the driver circuit structured and arranged to control the slew rate of the output signal;
generating a functional representation of a delay circuit coupled to the output signal of the driver circuit, the delay circuit having a delay proportional to a desired target slew rate of the output signal;
generating a functional representation of a first comparator for detecting when the output signal rises through a specified level;
generating a functional representation of a second comparator for detecting when the output signal falls through a second specified level; and
generating a functional representation of a phase detector coupled to outputs of the first and second comparators and to an output of the delay circuit, for aligning the phases (voltage-time relationships) of the comparator outputs with the phases of delayed comparator outputs by adjusting the slew rate of the output signal,
wherein the phase detector is coupled to inverted outputs of the first and second comparators.