Granted Patent B2

US 12,461,143 · App. 18/421,199 · Granted Nov 4, 2025

Inventors: Eyal Fayneh (Givatayim, IL); Yahel David (Kibbutz Gazit, IL); Evelyn Landman (Haifa, IL)

Assignee: PROTEANTECS LTD.

G01R31/2856G01R31/2882

Abstract

Claims (46)

1 . A device for failure risk measurement in a semiconductor Integrated Circuit (IC), the device comprising:

a plurality of data-change pulse generators, each data-change pulse generator being configured, when a signal from a respective data path and/or control logic circuit of the semiconductor IC changes, to generate a pulse of a preset time duration on a respective output path, wherein the data paths and/or control logic circuits of the semiconductor IC have a common clock;

a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;

an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby; and

a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.

2 . The device of claim 1 , wherein the signal combiner comprises logic circuitry configured to receive the output paths from the plurality of data-change pulse generators and provide a combined output path using one or more of: a logical OR operation; and a multiplexing operation.

3 . The device of claim 1 , wherein each data-change pulse generator comprises:

a signal splitter, coupled to the respective data path and/or control logic circuit of the semiconductor IC and configured to split a signal received from the respective data path and/or control logic circuit of the semiconductor IC between a first test path and a second test path;

a delay circuit, configured to delay a signal on the first test path by the preset time duration and provide a delayed first test path signal thereby; and

pulse generator logic, configured to receive the delayed first test path signal at a first input and a signal on the second test path at a second input, an output of the pulse generator logic providing the output path of the data-change pulse generator.

4 . The device of claim 3 , wherein each data-change pulse generator further comprises:

a device input buffer, configured to receive a signal from the respective data path and/or control logic circuit of the semiconductor IC and provide the received signal to the signal splitter.

5 . The device of claim 1 , further comprising:

a compensatory delay circuit, configured to receive the common clock and to provide a delayed clock signal to clock the device state element.

6 . The device of claim 5 , wherein the compensatory delay circuit is configured to introduce a delay of a time duration approximately equal to a propagation delay from the data path and/or control logic circuit of the semiconductor IC to the data input of the device state element.

7 . The device of claim 5 , wherein the compensatory delay circuit comprises an OR gate configured to receive the common clock on both first and second inputs.

8 . The device of claim 1 , wherein each data path is defined by a signal path of combinatorial or control logic of the semiconductor IC and/or an input to a respective data path state element that is clocked by the common clock.

9 . The device of claim 1 , further comprising:

a controller, configured to set the configurable time duration to one of each a group of discrete time duration values for each measurement of the device.

10 . The device of claim 9 , wherein the controller is further configured to change the configurable time duration between measurements of the device, to determine a margin measurement for at least a portion of the semiconductor IC thereby.

11 . The device of claim 9 , wherein the group of discrete time duration values span up to a period of the common clock.

12 . A semiconductor Integrated Circuit (IC), comprising:

logic circuitry, defining a plurality of data paths and/or control logic circuits having a common clock;

a device for failure risk measurement, comprising:

a plurality of data-change pulse generators, each configured to receive a signal from a respective one of the plurality of data paths and/or control logic circuits and to generate a pulse on a respective output path when the received signal changes;

a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;

an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby; and

a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.

13 . The semiconductor IC of claim 12 , wherein the logic circuitry comprises a plurality of logic cones or a plurality of combinatorial or control logic circuits, each of the plurality of data paths and/or control logic circuits being associated with a respective one of the plurality of logic cones or the plurality of combinatorial or control logic circuits.

14 . The semiconductor IC of claim 13 , wherein each of the plurality of logic cones comprises a respective cone output state element having a data input and wherein each data path is defined by the data input of an associated cone output state element.

15 . A method for failure risk measurement in a semiconductor Integrated Circuit (IC), the method comprising:

for each of a plurality of data paths and/or control logic circuits of the semiconductor IC, generating a pulse of a preset time duration on a respective output path when a signal from the respective data path and/or control logic circuit of the semiconductor IC changes, the plurality of data paths and/or control logic circuits of the semiconductor IC having a common clock;

combining the output paths from the plurality of data-change pulse generators, to provide a combined output path thereby;

delaying a signal on the combined output path by a configurable time duration, to provide a delayed combined output path signal thereby; and

outputting a failure risk measurement signal from a device state element that is clocked by a signal based on the common clock, the delayed combined output path signal being received at a data input of the device state element.

16 . The method of claim 15 , wherein the failure risk measurement signal is indicative of whether a timing margin of the semiconductor IC is within a certain range of the configurable time duration.

17 . The method of claim 16 , wherein the certain range is at least partly defined by the preset time duration of the pulse.

18 . The method of claim 15 , wherein the steps of generating, combining, delaying and outputting define a measurement process using a specific configurable time duration, the method further comprising:

performing the measurement process for a plurality of measurement instances, each of the plurality of measurement instances using a specific configurable time duration; and

determining an indication of a timing margin of the semiconductor IC based on the respective failure risk measurement signal of each of the plurality of measurement instances.

19 . The method of claim 18 , wherein the respective specific configurable time duration for each of the plurality of measurement instances is selected from a group of discrete time duration values and/or according to a predetermined sequence.

20 . A non-transitory computer readable medium having stored thereon a computer-readable encoding of a device for failure risk measurement in a semiconductor Integrated Circuit (IC), the computer-readable encoding of the loopback testing system comprising encodings of:

a plurality of data-change pulse generators, each data-change pulse generator being configured, when a signal from a respective data path and/or control logic circuit of the semiconductor IC changes, to generate a pulse of a preset time duration on a respective output path, each of the data paths and/or control logic circuits of the semiconductor IC having a common clock;

a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;

an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby; and

a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.

Assignments (1)

Continuity (1)

References Cited (330)