Performing static timing analysis of an integrated circuit design using dummy edge modeling
View Patent ↗An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by creating a dummy clock edge that is on the same edge as the data launch signal, and allowing the timing tool to compute the slack improvement using its native functions. The slack improvement is then multiplied by a conversion factor, and the result is used to adjust the slack. The apparatus and method give credit for slack in common blocks automatically, thereby allowing a large number of pessimistic slack values to be automatically corrected and reducing the workload of an integrated circuit designer in addressing the timing problems in an integrated circuit design.
1. A computer-implemented method for performing static timing analysis on an integrated circuit design, the method comprising the steps of:
identifying, by using a computer, a first logic block in the integrated circuit design that includes a clock test signal and a data launch signal that occur on opposite edges;
calculating slack between the clock test signal and the data launch signal;
creating a dummy clock test signal on the first logic block in a manner that the dummy clock test signal and the data launch signal occur on the same edge;
automatically identifying at least one common block through which both the clock test signal and the data launch signal pass before reaching the first logic block; and
adjusting the slack according to delay characteristics through the at least one common block.
2. The method of claim 1 wherein the step of adjusting the slack comprises the steps of:
(A) determining a difference between fastest and slowest delay through the at least one common block;
(B) multiplying the difference in (A) by a correction factor; and
(C) adjusting the slack by the result of the calculation in (B).
3. A computer-implemented method for performing static timing analysis on an integrated circuit design, the method comprising the steps of:
identifying, by using a computer, a first logic block in the integrated circuit design that includes a first clock test signal and data launched by a first data launch signal, where the first clock test signal and the first data launch signal occur on the same edge;
calculating a first slack number corresponding to slack between the first clock test signal and the data launched by the first data launch signal;
identifying a second logic block in the integrated circuit design that includes a second clock test signal and data launched by a second data launch signal where the second clock test signal and the second data launch signal occur on opposite edges;
calculating a second slack number corresponding to slack between the second clock test signal and the data launched by the second data launch signal;
creating a dummy clock test edge at the second logic block so the dummy clock test edge and the second data launch signal occur on the same edge;
automatically identifying a first set of common blocks through which both the first clock test signal and the first data launch signal pass before reaching the first logic block;
automatically adjusting the first slack number according to delay characteristics through the first set of common blocks;
automatically identifying a second set of common blocks through which both the second clock test signal and the second data launch signal pass before reaching the second logic block; and
automatically adjusting the second slack number according to delay characteristics through the second set of common blocks.
4. The method of claim 3 wherein the step of automatically adjusting the first slack number comprises the steps of:
(A) determining a difference between fastest and slowest delay through the first set of common blocks; and
(B) adjusting the first slack number by the difference calculated in (A).
5. The method of claim 3 wherein the step of automatically adjusting the second slack number comprises the steps of:
(A) determining a difference between fastest and slowest delay through the second set of common blocks;
(B) multiplying the difference in (A) by a correction factor; and
(C) adjusting the second slack number by the result of the calculation in (B).
6. The method of claim 3 wherein the step of automatically adjusting the second slack number comprises the step of defining at least one user delta adjust parameter for the second clock test signal.