Semiconductor integrated circuit and method of detecting fail path thereof
Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.
1. A semiconductor integrated circuit, comprising:
a data register that receives input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated;
a first comparing unit that compares write data written in a memory cell with the write expectation value; and
a second comparing unit that compares read data read from the memory cell with the read expectation value,
wherein the first and second comparing units are coupled with the data register to be simultaneously driven according to a test mode signal.
2. The semiconductor integrated circuit of claim 1 ,
wherein the data register comprises:
a first expectation value storage unit that receives a test mode activation signal and the input data to output the write expectation value; and
a second expectation value storage unit that receives the test mode activation signal, the input data, data input clock signals, and data output clock signals to output the read expectation value.
3. The semiconductor integrated circuit of claim 2 ,
wherein the first expectation value storage unit comprises a delayer, and the first expectation value storage unit delays the input data to align a comparing timing between the input data and the write data.
4. The semiconductor integrated circuit of claim 2 ,
wherein the second expectation value storage unit comprises a plurality of latch units, each of which latches the input data synchronized with the data input clock signal and outputs the input data synchronized with the data output clock signal.
5. The semiconductor integrated circuit of claim 1 ,
wherein the first comparing unit outputs an activated first detection signal, when the write data and the write expectation value are coincided with each other.
6. The semiconductor integrated circuit of claim 1 ,
wherein the second comparing unit outputs an activated second detection signal, when the read data and the read expectation value are coincided with each other.
7. A semiconductor integrated circuit, comprising:
a data register that receives input data provided from a data input buffer to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated;
a first comparing unit that compares the write expectation value with write data received to a write driver to output a first detection signal, thereby detecting whether a fail occurs on a path between the data input buffer and the write driver according to a logic level of the first detection signal; and
a second comparing unit that compares the read expectation value with read data provided from a data sense amplifier to output a second detection signal, thereby detecting whether a fail occurs on a path between the write driver and the data sense amplifier according to a logic level of the second detection signal,
wherein the first and second comparing units are coupled with the data register to be simultaneously driven according to a test mode signal.
8. The semiconductor integrated circuit of claim 7 ,
wherein the data register comprises:
a first expectation value storage unit that receives a test mode activation signal and the input data to output the write expectation value; and
a second expectation value storage unit that receives the test mode activation signal, the input data, data input clock signals, and data output clock signals to output the read expectation value.
9. The semiconductor integrated circuit of claim 8 ,
wherein the first expectation value storage unit comprises a delayer that aligns comparison timing between the input data and the write data.
10. The semiconductor integrated circuit of claim 8 ,
wherein the second expectation value storage unit comprises a plurality of latch units, each of which latches the input data synchronized with the data input clock signal and outputs the input data synchronized with the data output clock signal.
11. The semiconductor integrated circuit of claim 7 ,
wherein the first comparing unit outputs the first detection signal activated, when the write data and the write expectation value are coincided with each other.
12. The semiconductor integrated circuit of claim 7 ,
wherein the second comparing unit outputs the second detection signal activated, when the read data and the read expectation value are coincided with each other.
13. A semiconductor integrated circuit, comprising:
a detecting block that receives input data and stores the input data as a write expectation value and a read expectation value when a test mode is activated, and detects fail occurrence in the semiconductor integrated circuit by comparing write data written in a memory cell with the write expectation value and determining whether the write data and the write expectation value are coincided with each other, and by comparing read data read from the memory cell with the read expectation value and determining whether the read data and the read expectation value are coincided with each other, thereby narrowing a fail analysis path range,
wherein the comparing of the write data and the comparing of the read data are simultaneously performed according to a test mode signal.
14. The semiconductor integrated circuit of claim 13 ,
wherein the detecting block comprises:
a data register that receives the input data to generate and store the write expectation value and the read expectation value, during a period in which the test mode is activated;
a first comparing unit that compares the write data written in the memory cell with the write expectation value; and
a second comparing unit that compares the read data read from the memory cell with the read expectation value.
15. The semiconductor integrated circuit of claim 14 ,
wherein the data register comprises:
a first expectation value storage unit that receives a test mode activation signal and the input data to output the write expectation value; and
a second expectation value storage unit that receives the test mode activation signal, the input data, data input clock signals, and data output clock signals to output the read expectation value.
16. The semiconductor integrated circuit of claim 15 ,
wherein the first expectation value storage unit comprises a delayer, and
the first expectation value storage unit delays the input data to align comparison timing between the input data and the write data.
17. The semiconductor integrated circuit of claim 15 ,
wherein the second expectation value storage unit comprises a plurality of latch units, each of which latches the input data synchronized with the data input clock signal and outputs the input data synchronized with the data output clock signal.
18. The semiconductor integrated circuit of claim 14 ,
wherein the first comparing unit outputs an activated first detection signal, when the write data and the write expectation value are coincided with each other.
19. The semiconductor integrated circuit of claim 14 ,
wherein the second comparing unit outputs an activated second detection signal, when the read data and the read expectation value are coincided with each other.
20. A method of detecting a fail path of a semiconductor integrated circuit, the method comprising:
receiving input data and generating a write expectation value and a read expectation value, during a period in which a test mode is activated;
comparing write data written in a memory cell with the write expectation value to output a first detection signal, thereby determining whether a fail occurs; and
comparing read data read from the memory cell with the read expectation value to output a second detection signal, thereby determining whether a fail occurs,
wherein the comparing of the write data and the comparing of the read data are simultaneously performed according to a test mode signal.
21. The method of claim 20 ,
wherein the input data is a signal that is provided by a data input buffer,
the write data is a signal that is received to a write driver, and
the read data is a signal that is provided from a data sense amplifier.
22. The method of claim 21 ,
wherein, when the write expectation value and the write data are not coincided with each other, the first detection signal, which is inactivated, is output.
23. The method of claim 22 ,
wherein the inactivated first detection signal indicates that a fail exists on a path between the data input buffer and the write driver.
24. The method of claim 21 ,
wherein, when the read expectation value and the read data are not coincided with each other, the second detection signal, which is inactivated, is output.
25. The method of claim 24 ,
wherein the inactivated second detection signal indicates that a fail exists on a path between the write driver and the data sense amplifier.