Circuit structure to measure outliers of process variation effects

1. An integrated circuit for testing one or more transistors, the integrated circuit comprising:

a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes:

two ring oscillators, wherein each ring oscillator includes an odd number of inverter stages, wherein the inverter stages include the one or more transistors, wherein each ring oscillator is associated with an output signal;

a first multiplexer configured to receive the output signals associated with the two ring oscillators and provide as an output one of the output signals associated with the two ring oscillators; and

a first divide-by-two circuit, wherein the first divide-by-two circuit is configured to receive the output from the first multiplexer and provide an oscillating signal that is at half of the frequency of the output from the first multiplexer;

a multiplexer stage including a plurality of multiplexers, wherein each multiplexer of the multiplexer stage is configured to receive an output from a corresponding ring oscillator macro circuit;

a divide-by-two circuit stage including a plurality of divide-by-two circuits, wherein each divide-by-two circuit is configured to receive an output from each of the multiplexers of the multiplexer stage;

a second multiplexer configured to receive an output from each of the divide-by-two circuits in the divide-by-two circuit stage;

a second divide-by-two circuit configured to receive an output from the second multiplexer; and

a frequency measurement circuit configured to measure the frequency of an output from the second divide-by-two circuit.

2. The integrated circuit of claim 1 , wherein the frequency measurement circuit includes a first counter and a second counter.

3. The integrated circuit of claim 2 , wherein the first counter increments at every positive transition of the output from the second divide-by-two circuit.

4. The integrated circuit of claim 2 , wherein the second counter increments at every positive transition of a reference clock.

5. The integrated circuit of claim 1 , wherein each inverter stage includes an inverter.

6. The integrated circuit of claim 1 , wherein each inverter stage includes a NAND gate.

7. The integrated circuit of claim 6 , wherein the NAND gate is a NAND2 gate.

8. The integrated circuit of claim 1 , wherein the inverter stage can be a NAND3 circuit.

9. The integrated circuit of claim 1 , wherein the inverter stage can be an inverter with m-stacked N-MOS transistors and m-stacked P-MOS transistors, where m refers to an integer ≥2.

10. The integrated circuit of claim 1 , wherein the inverter stage can be an inverter with a plurality of N-MOS and P-MOS transistors in parallel with each other.

11. An integrated circuit for testing one or more transistors, the integrated circuit comprising:

a first shift register including a plurality of devices-under-test (DUT), wherein the plurality of DUTs are dynamic latches including the one or more transistors;

a second shift register including a plurality of static latches;

a first multiplexer configured to receive outputs from each of the plurality of DUTs;

a second multiplexer configured to receive outputs from each of the plurality of static latches; and

a comparator configured to compare an output from the first multiplexer with an output from the second multiplexer.

12. The integrated circuit of claim 11 , wherein each DUT includes one of a low threshold voltage transistor and an ultra-low voltage threshold transistor.

13. The integrated circuit of claim 11 , wherein the dynamic latches are transmission-gate dynamic latches.

14. The integrated circuit of claim 11 , wherein each DUT includes a respective 2-to-1 multiplexer.

15. The integrated circuit of claim 11 , wherein the comparator is an Exclusive OR (XOR) gate.

16. The integrated circuit of claim 11 , wherein more than one of the plurality of DUTs receives the same data signal.