Dynamic critical path detector for digital logic circuit paths
View Patent ↗Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.
1. A method in a computer-aided design system for generating a functional design model of a dynamic critical path detector, the method comprising:
generating, by a processor, a functional representation of a first latch arranged in a region of a critical path and structured to receive a data signal;
generating a functional representation of a second latch arranged in a region of the critical path;
generating a functional representation of a delay element to couple a delayed version of the data signal to the second latch; and
generating a functional representation of a comparator device positioned between an output and input of two components of the second latch and structured and arranged to compare outputs of the first and second latches,
wherein:
a miscompare from the comparator device is indicative of an approaching timing failing condition and the miscompare occurs when the output of the first latch and the output of the second latch occur within different clock pulses; and
the output of the first latch and the output of the second latch occur within different clock pulses when the output of the first latch occurs before a leading edge of a first clock pulse and the output of the second latch occurs after a trailing edge of a second clock pulse.
2. The method of claim 1 , wherein the functional design model comprises a netlist, which describes the circuit.
3. The method of claim 1 , wherein the functional design model e resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The method of claim 1 , wherein the functional design model includes at least one of test data files, characterization data, verification data, or design specifications.
5. A method in a computer-aided design system for generating a functional design model of a dynamic critical path detector, the method comprising:
generating, by a processor, a functional representation of a first latch pair and second latch pair near a critical path, wherein the first latch pair has an input comprising a data value on the critical path;
generating a functional representation of a delay element to generate a delayed data value from the data value and to latch the delayed data value in the second latch pair;
generating a functional representation of a comparator device to compare the data value with the delayed data value to determine whether the critical path comprises a timing failure condition; and
generating a functional representation of a device to execute a predetermined corrective measure for the critical path,
wherein:
a miscompare from the comparator device occurs when the data value and the delayed data value occur within different clock pulses and the miscompare is indicative of the timing failure condition; and
the data value and the delayed data value occur within different clock pulses when the data value occurs before a leading edge of a first clock pulse and the delayed data value occurs after a trailing edge of a second clock pulse.
6. The method of claim 1 , wherein:
the first latch is a first latch pair; and
the second latch is a second latch pair.
7. The method of claim 6 , wherein the delay element is single delay element at the input of the second latch.
8. The method of claim 7 , wherein the single delay element is positioned at an input side of a latch of the second latch pair.
9. The method of claim 8 , wherein the two components of the second latch pair is a first latch and a second latch, and the comparator device is positioned between the first and second latch of the second latch pair.
10. The method of claim 9 , wherein the comparator device is positioned between an output of the first latch of the second latch pair and an input of the second latch of the second latch pair.
11. The method of claim 10 , wherein the comparator device is positioned at an output of the first latch of the first latch pair.
12. The method of claim 10 , wherein the first latch pair are flip flop latches and the second latch pair are delayed flip flops latches.
13. The method of claim 11 , wherein a second latch of the first latch pair and second latch pair are coupled together.
14. The method of claim 6 , wherein the first latch pair are flip flop latches and the second latch pair are delayed flip flops latches.
15. The method of claim 6 , wherein a second latch of the first latch pair and second latch pair are coupled together.
16. The method of claim 1 , wherein the delay element is single delay element at the input of the second latch.
17. The method of claim 5 , wherein the comparator device is positioned between an output of a first latch of the first latch pair and the second latch pair, and an input of a second latch of the second latch pair.
18. The method of claim 5 , wherein the delay element is a single delay element at an input of the second latch pair.
19. The method of claim 5 , wherein the first latch pair is a flip flop latch pair and the second latch pair is a delayed flip flop latch pair.
20. The method of claim 5 , wherein the first latch pair and second latch pair are coupled together.