Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller
A method of testing a data transmission and reception system comprises sending a test signal from a transmitter ( 14 ) of the system to a receiver ( 12 ) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.
1. A method of testing a data transmission and reception system, the method comprising:
sending a test signal from a transmitter of the system to a receiver of the system;
analyzing the received test signal;
varying a duty cycle relationship between the received test signal and a timing signal used by the receiver, wherein said varying the duty cycle relationship further comprises:
splitting the received test signal sent by the transmitter into first and second branches,
combining signals processed by the first and second branches in an AND gate to provide a reduced duty cycle, and
combining signals processed by the first and second branches in an OR gate to provide an increased duty cycle;
analyzing an effect of the duty cycle variation; and
selecting, with a multiplexer, between either the increased duty cycle or the decreased duty cycle based upon a binary multiplexer control signal provided by a test register.
2. The method as claimed in claim 1 , wherein the duty cycle of the test signal is varied in a path between an output of the transmitter and an input of the receiver.
3. The method as claimed in claim 1 , wherein delaying the signal of one branch further comprises:
adding a programmable amount of load.
4. The method as claimed in claim 1 , wherein delaying the signal of one branch further comprises:
using a programmable drive strength.
5. The method as claimed in claim 1 , further comprising:
low-pass filtering the signal provided to the receiver; and
measuring a dc voltage which represents the duty cycle.
6. The method as claimed in claim 1 , further comprising:
sampling the signal provided to the receiver; and
counting the number of sampled ‘1’s and/or ‘0’ s, wherein the ratio of counted ‘1’ s to the total number of samples represents the duty cycle.
7. The method as claimed in claim 1 , wherein the analysis comprises bit error ratio measurement.
8. The method as claimed in claim 1 , wherein analyzing the received signal comprises:
providing a pass or fail indication based on the duty cycle variation and a measured receiver error rate.
9. The method as claimed in claim 1 , wherein analyzing the received signal comprises:
calculating the jitter from the duty cycle variation and a measured receiver error rate.
10. The method as claimed in claim 1 , further comprising: performing clock recovery from received data in the receiver; and
using the recovered clock to interpret the received data.
11. The method as claimed in claim 10 , further comprising:
performing clock recovery from rising and falling edges of the received data.
12. The method as claimed in claim 10 , further comprising:
performing clock recovery from the rising or falling edges of the received data; and
analyzing the effect of duty cycle variation for a recovered clock using the rising edges of the received data and for a recovered clock using the falling edges of the received data.
13. An apparatus for testing a data transmission and reception system, comprising:
a circuit configured to generate a test signal for transmission;
a circuit configured to vary a duty cycle relationship between the test signal and a timing signal used by a receiver of the system,
wherein said varying the duty cycle relationship comprises
varying a duty cycle of the test signal by splitting the test signal sent by a transmitter into first and second branches,
combining signals processed by the first and second branches in an AND gate to provide a reduced duty cycle,
combining signals processed by the first and second branches in an OR gate to provide an increased duty cycle, and
selecting, with a multiplexer, between either the increased duty cycle or the decreased duty cycle based upon a binary multiplexer control signal provided by a test register; and
a circuit configured to analyze a received signal, which includes the transmitted signal after an effect of a duty cycle variation.
14. The apparatus as claimed in claim 13 , wherein the analysis circuit comprises a bit error ratio measurement circuit.
15. The apparatus as claimed in claim 13 , wherein the duty cycle varying circuit comprises:
a splitter configured to split a transmitter output into two branches; and
a delay element configured to delay the signal of one branch by a programmable amount of time.
16. The apparatus as claimed in claim 15 , wherein the delay element comprises a variable load.
17. The apparatus as claimed in claim 13 , further comprising:
a circuit configured to determine the duty cycle variation.
18. The apparatus as claimed in claim 17 , wherein the determining circuit comprises
a low-pass filter; and
a circuit configured to measure a dc voltage which represents the duty cycle.
19. The apparatus as claimed in claim 13 , further comprising:
a circuit configured to recover a clock signal from the received signal.
20. The apparatus as claimed in claim 19 , wherein the clock recovery circuit uses the rising or falling edges of the received data, and the apparatus further comprises:
a circuit configured to select the rising or falling edges for clock recovery.
21. A data transmission and reception system, comprising:
a transmitter;
a receiver; and
a testing apparatus configured for implementing a method of testing a data transmission and reception system, the method comprising:
sending a test signal from a transmitter of the system to a receiver of the system,
analyzing the received test signal,
varying a duty cycle relationship between the received test signal and a timing signal used by the receiver, wherein said varying the duty cycle relationship further comprises:
varying a duty cycle of the received test signal by splitting the received test signal sent by the transmitter into first and second branches,
combining signals processed by the first and second branches in an AND gate to provide a reduced duty cycle;
combining signals processed by the first and second branches in an OR gate to provide an increased duty cycle;
analyzing an effect of the duty cycle variation;
performing clock recovery from received data in the receiver;
using the recovered clock to interpret the received data;
performing clock recovery from rising or falling edges of the received data;
analyzing the effect of the duty cycle variation for the recovered clock using the rising edges of the received data and the falling edges of the received data; and
selecting, with a multiplexer, between either the increased duty cycle or the decreased duty cycle based upon a binary multiplexer control signal provided by a test register.