Test circuit and method

1. A test circuit comprising:

an oscillator configured to generate an oscillation signal;

a device-under-test (DUT) configured to output an alternating current (AC) signal based on the oscillation signal;

a first detection circuit configured to generate a first direct current (DC) voltage having a first value based on the oscillation signal; and

a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

2. The test circuit of claim 1 , wherein the oscillator comprises a ring oscillator configured to generate the oscillation signal as a radio frequency (RF) signal.

3. The test circuit of claim 2 , further comprising an isolation circuit coupled between the oscillator and the DUT, wherein the isolation circuit comprises a switched resistor array and a switched capacitor array configured as a low-pass filter.

4. The test circuit of claim 1 , wherein the oscillator comprises an inductor-capacitor (LC) resonator configured to generate the oscillation signal as a millimeter-wave signal.

5. The test circuit of claim 4 , wherein the oscillator further comprises a switched resistor array coupled in series with the LC resonator.

6. The test circuit of claim 4 , further comprising an inverter coupled between the oscillator and the DUT.

7. The test circuit of claim 1 , wherein

the first detection circuit comprises an input terminal coupled to an input terminal of the DUT, each of the first detection circuit and the DUT thereby being configured to receive an AC input signal based on the oscillation signal,

the second detection circuit comprises an input terminal coupled to an output terminal of the DUT, the second detection circuit thereby being configured to receive the AC signal,

the first detection circuit is configured to generate the first DC voltage by decreasing the first value responsive to an increase in an amplitude of the AC input signal, and

the second detection circuit is configured to generate the second DC voltage by decreasing the second value responsive to an increase in an amplitude of the AC signal.

8. The test circuit of claim 1 , further comprising a load circuit coupled to an output terminal of the DUT.

9. An integrated circuit (IC) comprising:

a device-under-test (DUT) coupled between a first node and a second node on a semiconductor wafer; and

a built-in-self-test (BIST) circuit comprising:

an oscillator configured to generate an oscillation signal, wherein the BIST circuit is configured to output a first alternating current (AC) signal on the first node, the first AC signal having a frequency of the oscillation signal;

a first detection circuit configured to output a first direct current (DC) voltage on a first pad at a top surface of the semiconductor wafer, the first DC voltage having a first value based on the first AC signal; and

a second detection circuit configured to output a second DC voltage on a second pad at the top surface of the semiconductor wafer, the second DC voltage having a second value based on a second AC signal output by the DUT on the second node.

10. The IC of claim 9 , further comprising an isolation circuit coupled between the oscillator and the first node,

wherein at least one of the oscillator or the isolation circuit comprises a switched resistor array comprising one or more control terminals coupled to a corresponding one or more pads at the top surface of the semiconductor wafer in addition to the first and second pads.

11. The IC of claim 9 , wherein

the DUT comprises an inverting amplifier comprising a switched transistor array configured to control a gain of the inverting amplifier, and

the switched transistor array comprises one or more control terminals coupled to a corresponding one or more pads at the top surface of the semiconductor wafer in addition to the first and second pads.

12. The IC of claim 9 , wherein

the DUT comprises a common-source amplifier comprising a gate voltage node configured to control a gain of the common-source amplifier, and

the gate voltage node is coupled to a third pad at the top surface of the semiconductor wafer.

13. The IC of claim 9 , wherein

each of the first and second detection circuits comprises a gate voltage node configured to control a gain value of the corresponding first or second detection circuit, and

each gate voltage node is coupled to a corresponding pad at the top surface of the semiconductor wafer in addition to the first and second pads.

14. The IC of claim 9 , wherein

the first detection circuit is configured to generate the first DC voltage by decreasing the first value responsive to an increase in an amplitude of the first AC signal at the frequency of the oscillation signal, and

the second detection circuit is configured to generate the second DC voltage by decreasing the second value responsive to an increase in an amplitude of the second AC signal at the frequency of the oscillation signal.

15. The IC of claim 9 , wherein each of the first and second pads is located at the top surface of the semiconductor wafer either in a scribe line or in a process-control-monitor (PCM) die.

16. A method of performing a direct current (DC) test, the method comprising:

electrically accessing a pad array of a semiconductor wafer;

using an oscillator on the semiconductor wafer to generate a first alternating current (AC) signal;

using a device-under-test (DUT) on the semiconductor wafer to generate a second AC signal based on the first AC signal; and

outputting first and second DC voltages to the pad array, the first DC voltage having a first value based on an amplitude of the first AC signal and the second DC voltage having a second value based on an amplitude of the second AC signal.

17. The method of claim 16 , wherein the electrically accessing the pad array comprises electrically accessing the pad array in one or more scribe lines or in a process-control-monitor (PCM) die.

18. The method of claim 16 , wherein the using the oscillator on the semiconductor wafer to generate the first AC signal comprises:

providing a plurality of DC voltage levels to the pad array;

in response to the plurality of DC voltage levels, using the oscillator to generate an oscillation signal; and

using an isolation circuit to generate the first AC signal from the oscillation signal.

19. The method of claim 16 , wherein the outputting the first and second DC voltages to the pad array comprises:

providing a plurality of DC voltage levels to the pad array; and

in response to the plurality of DC voltage levels,

controlling a first gain value of a first detection circuit configured to generate the first DC voltage based on the first AC signal, and

controlling a second gain value of a second detection circuit configured to generate the second DC voltage based on the second AC signal.

20. The method of claim 16 , wherein

the using the DUT on the semiconductor wafer to generate the second AC signal based on the first AC signal comprises setting a first gain value of the DUT by providing a first plurality of DC voltage levels to the pad array, and

the method further comprises:

setting a second gain value of the DUT by providing a second plurality of DC voltage levels to the pad array;

using the DUT on the semiconductor wafer to generate a third AC signal based on the first AC signal and the second gain value; and

outputting a third DC voltage to the pad array, the third DC voltage having a third value based on an amplitude of the third AC signal.