Integrated circuit I/O integrity and degradation monitoring
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
1. An input/output (I/O) block for a semiconductor integrated circuit (IC), the I/O block comprising:
at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and
an I/O sensor coupled to the at least one signal path and configured to generate an output signal indicative of at least one of:
(a) a timing difference between: the signal edge slope for a first signal path of the at least one signal path, and the signal edge slope for a second, distinct signal path of the at least one signal path, and
(b) an eye pattern parameter for one or more of the at least one signal path.
2. The I/O block of claim 1 , wherein;
the least one I/O buffer comprises a transmission buffer,
the first signal path is coupled to an output of the transmission buffer that is coupled to the communication channel,
the first signal path being further coupled to the remote I/O block via a first connection bump, and
the output signal of the I/O sensor being further indicative of a quality of the first connection bump.
3. The I/O block of claim 2 , wherein:
the least one I/O buffer is configured to use differential signaling across the communication channel,
the transmission buffer is configured to produce two differential outputs,
the first signal path is coupled to a first differential output of the two differential outputs;
the second signal path is: coupled to the remote I/O block via a second connection bump, and coupled to a second differential output of the two differential outputs, and
the output signal of the I/O sensor being further indicative of a quality of the second connection bump.
4. The I/O block of claim 2 , wherein the at least one signal path comprises at least one of:
(a) a signal path that is coupled to an input of the transmission buffer; and
(b) a signal path that is coupled to the remote I/O block via an interconnect and a connection bump between the transmission buffer and the interconnect,
wherein the output signal of the I/O sensor being further indicative of a quality of the first connection bump.
5. The I/O block of claim 1 , further comprising:
a differential buffer, configured to output a difference between a differential buffer input signal, received on a path coupled to the communication channel, and a fixed level signal,
wherein a signal path of the at least one signal path is coupled to the output of the differential buffer.
6. The I/O block of claim 5 , wherein the fixed level signal is a voltage fixed at a predetermined proportion of a DC power supply voltage for the IC, optionally wherein:
the predetermined proportion is dynamically adjusted; or
the predetermined proportion is 75%.
7. The I/O block of claim 1 , wherein the at least one I/O buffer comprises a reception buffer having an input that is coupled to the communication channel, a signal path of the at least one signal path being coupled to an output of the reception buffer.
8. The I/O block of claim 7 , wherein the input to the reception buffer is coupled to the remote I/O block via an interconnect and a connection bump between the interconnect and remote I/O block, the output signal of the I/O sensor being further indicative of a quality of the connection bump.
9. The I/O block of claim 1 , wherein the communication channel is configured to carry a differential signal via two signal lines, a first signal path of the at least one signal path being coupled to a first signal line and a second signal path of the at least one signal path being coupled to a second signal line.
10. The I/O block of claim 1 , wherein the I/O sensor comprises:
a first input port;
a second input port;
a third input port coupled to a second signal path; and
a selector, configured to couple the first signal path to either the first input port or the second input port in response to a received selection signal, such that the output signal of the I/O sensor is selectively indicative of a timing difference between (a) the signal edge for the second signal path, and (b) the signal edge for the first signal path either through the first input port or through the second input port.
11. The I/O block of claim 1 , wherein the eye pattern parameter comprises one or more of: eye width; eye height; eye width jitter; and eye height fluctuation.
12. The I/O block of claim 1 , wherein the output signal comprises a pulse having a width indicative of: a timing difference between the signal edge for the first signal path and the signal edge for the second signal path; or the eye pattern parameter.
13. The I/O block of claim 1 , further comprising at least one of:
a performance optimizer configured to adjust a parameter of the at least one I/O buffer based on the output signal of the I/O sensor; and
a repair controller configured to adjust a configuration of the I/O buffer based on the output signal of the I/O sensor.
14. The I/O block of claim 13 , wherein the repair controller is configured, in response to the output signal of the I/O sensor, to perform at least one of:
disable a part or a whole of the IC;
cause a lane remapping of at least part of the IC; and
adjust a transmission buffer strength within the IC, based on at least one of: an instantaneous temperature of the IC, and voltage of the IC.
15. The I/O block of claim 1 , further comprising:
a time-to-digital converter, configured to receive a timing signal derived from the output signal of the I/O sensor and to provide a digital time signal based on the timing signal.
16. A semiconductor integrated circuit (IC), comprising the I/O block of claim 1 .
17. The semiconductor IC of claim 16 , wherein the I/O sensor is configured to communicate the output signal externally of the semiconductor IC.
18. The semiconductor IC of claim 16 , further comprising:
a filtered counter block, configured to,
receive a time signal based on the output signal of the I/O sensor,
compare the received time signal against a threshold, and
based on the comparison, identify exceptional or outlier readouts from the I/O sensor.
19. The semiconductor IC of claim 18 , wherein the filtered counter block is further configured to count at least one number of: a normal readouts from the I/O sensor, and a number of exceptional or outlier readouts from the I/O sensor.
20. A semiconductor IC system, comprising the semiconductor IC of claim 16 and further comprising at least one of:
an I/O profiling part, configured to generate at least one of an I/O profile and an I/O classification, based on the output signal of the I/O sensor; and
an Embedded Virtual Scope (EVS) part, configured to measure at least one of a signal amplitude and a signal slew-rate for a pin of the semiconductor IC, based on the output signal of the I/O sensor.
21. The semiconductor IC system of claim 20 , wherein the I/O profiling part is further configured to perform at least one of:
compare at least one of the I/O profile and the classification with family data for the semiconductor IC;
detect a systematic shift based on at least one of the I/O profile and the classification; and
detect outliers based on tester data.