Die-to-die connectivity monitoring
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
1. A multi-IC (Integrated Circuit) module comprising:
a first IC comprising a transmitter; and
a second IC interconnected to said first IC over an interconnect lane, wherein said second IC comprises:
a receiver,
an adjustable delay line configured to receive, from said receiver, a data signal that was transmitted by said transmitter of said first IC over the interconnect lane, and
processing logic configured to:
set said adjustable delay line to a plurality of time durations, to delay the data signal until a fail condition is detected, and
based on the detection of the fail condition, determine reliability of connectivity between the first and second ICs.
2. The multi-IC module of claim 1 , wherein said processing logic is further configured, in response to the determined reliability of connectivity, to repair the interconnect lane.
3. The multi-IC module of claim 1 , wherein said processing logic is further configured, in response to the determined reliability of connectivity, to adjust at least one of data throughput and clock rate of the multi-IC module.
4. The multi-IC module of claim 1 , wherein said first and second ICs are interconnected at least using one or more of:
(a) bumps;
(b) micro-bumps;
(c) pins;
(d) a Re-Distribution Layer (RDL) and Through Integrated Fan-Out Vias (TIVs);
(e) Through-Silicon Vias (TSVs); or
(f) pads.
5. The multi-IC module of claim 4 , wherein the determination of the reliability of connectivity comprises determining a resistance parameter of at least one of (a) through (f).
6. The multi-IC module of claim 4 , wherein the reliability of connectivity is affected by degradation of at least one of (a) through (f).
7. The multi-IC module of claim 1 , wherein the determination of the reliability of connectivity comprises determining a systematic effect parameter.
8. The multi-IC module of claim 1 , wherein the determination of the reliability of connectivity comprises determining a parameter indicating a symmetry of differential signals.
9. The multi-IC module of claim 1 , wherein the determination of the reliability of connectivity comprises determining clock duty cycle effects on eye width.
10. The multi-IC module of claim 1 , wherein the reliability of connectivity is affected by an open circuit.
11. The multi-IC module of claim 1 , wherein the reliability of connectivity is affected by a short circuit.
12. The multi-IC module of claim 1 , wherein the reliability of connectivity is affected by a bridge short.
13. The multi-IC module of claim 1 , wherein said processing logic is further configured to measure a margin, based on a minimum delay that caused the fail condition.
14. The multi-IC module of claim 1 , wherein said processing logic is further configured to determine a sum of minimum time durations which caused the fail condition.
15. The multi-IC module of claim 1 , wherein said processing logic is further configured, based on the detection of the fail condition, to measure a margin of the data signal.
16. The multi-IC module of claim 15 , wherein the margin measurement comprises at least one of:
a data signal setup time to clock rising edge;
a data signal setup time to clock falling edge;
a data signal hold time to clock rising edge; and
a data signal hold time to clock falling edge.
17. The multi-IC module of claim 1 , wherein said delay circuitry comprises:
a first state-element, configured to receive a first state-element input signal and to provide a first state-element output based on the first state-element input signal and a first clock input;
a second state-element, configured to receive a second state-element input signal and to provide a second state-element output based on the second state-element input signal and a second clock input; and
a multiplexing arrangement, configured selectively to apply one of:
the data signal as the input signal to the adjustable delay line, an output of the adjustable delay-line being provided as the first state-element input signal, the data signal being provided as the second state-element input signal, and a clock signal being provided as the first and second clock inputs; and
the clock signal as the input signal to the adjustable delay line, an output of the adjustable delay-line being provided as the first clock input, the data signal being provided as the first and second state-element input signals, and the clock signal being provided as the second clock input.
18. The multi-IC module of claim 17 , wherein said multiplexing arrangement is further configured to selectively apply, as the clock signal:
a positive clock signal; or
a negative clock signal that is the positive clock signal inverted.