Semiconductor device having stacked chips
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.
1. A semiconductor device comprising:
a first memory chip including:
a first NAND flash memory; and
a plurality of first vias extending in the first memory chip in a first direction perpendicular to one surface of the first memory chip, the first vias being arranged along a second direction parallel to the one surface of the first memory chip; and
a first dedicated chip stacked on the one surface of the first memory chip in the first direction, the first dedicated chip including at least one via extending in the first direction and connected to one of the first vias, and the first dedicated chip comprising a power supply chip including a pump circuit,
wherein the first memory chip and the first dedicated chip overlap when viewed in the first direction, and
wherein an output from the first dedicated chip is supplied to the first memory chip via the one of the first vias.
2. The semiconductor device according to claim 1 , further comprising:
a second memory chip stacked on the first memory chip such that one surface thereof faces the other surface of the first memory chip, the second memory chip including:
a second NAND flash memory; and
a plurality of second vias extending in the second memory chip in the first direction, the second vias being arranged along the second direction to overlap with the first vias when viewed in the first direction;
a third memory chip stacked on the second memory chip such that one surface thereof faces the other surface of the second memory chip, the third memory chip including:
a third NAND flash memory; and
a plurality of third vias extending in the third memory chip in the first direction, the third vias being arranged along the second direction to overlap with respective ones of the second vias when viewed in the first direction; and
a fourth memory chip stacked on the third memory chip such that one surface thereof faces the other surface of the third memory chip, the fourth memory chip including:
a fourth NAND flash memory,
wherein the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip overlap one another when viewed in the first direction.
3. The semiconductor device according to claim 2 , further comprising:
a second dedicated chip stacked on the one surface of the first memory chip in the first direction at one side of the first dedicated chip in the second direction, the second dedicated chip including at least one via extending in the first direction and connected to another one of the first vias, and the second dedicated chip including an interface circuit,
wherein the first memory chip and the second dedicated chip overlap when viewed in the first direction.
4. The semiconductor device according to claim 3 , wherein:
the first memory chip includes:
a first substrate through which the first vias extend, and
at least three first logical circuits formed on the first substrate,
the second memory chip includes:
a second substrate through which the second vias extend, and
at least three second logical circuits formed on the second substrate,
the third memory chip includes:
a third substrate through which the third vias extend, and
at least three third logical circuits formed on the third substrate,
the fourth memory chip includes:
a fourth substrate, and
at least three fourth logical circuits formed on the fourth substrate, first ones of the first to third logical circuits of the first to third memory chips are
each configured to perform a first logical operation on a first address input signal received at its respective chip, to thereby output a first address output signal,
second ones of the first to third logical circuits of the first to third memory chips are each configured to perform a second logical operation on a second address input signal received at its respective chip and the first address output signal transmitted within its respective chip, to thereby output a second address output signal, and
third ones of the first to third logical circuits of the first to third memory chips are each configured to activate its respective chip based on at least the second address output signal transmitted within its respective chip.
5. The semiconductor device according to claim 4 , wherein among the first to fourth memory chips, the first memory chip is nearest to the first dedicated chip and the second dedicated chip, and the fourth memory chip is farthest from the first dedicated chip and the second dedicated chip.
6. The semiconductor device according to claim 4 , wherein:
each of the first to fourth memory chips comprises:
a memory cell array, and
a peripheral circuit.
7. The semiconductor device according to claim 4 , wherein:
the first memory chip further includes at least two first wiring layers,
the second memory chip further includes at least two second wiring layers,
the third memory chip further includes at least two third wiring layers,
the fourth memory chip further includes at least two fourth wiring layers, and
the first to third vias of the first to third memory chips at least partially overlap with the second to fourth wiring layers of the second to fourth memory chips in the first direction, respectively.
8. The semiconductor device according to claim 7 , wherein:
input nodes of the first ones of the first to third logical circuits of the first to third memory chips are electrically connected to first ones of the first to third wiring layers of the first to third memory chips, respectively, and output nodes of the first ones of the first to third logical circuits of the first to third memory chips are electrically connected to first ones of the second to fourth vias of the second to fourth memory chips, respectively, and
input nodes of the second ones of the first to third logical circuits of the first to third memory chips are electrically connected to second ones of the first to third wiring layers of the first to third memory chips, respectively, and output nodes of the second ones of the first to third logical circuits of the first to third memory chips are electrically connected to second ones of the second to fourth vias of the second to fourth memory chips, respectively.
9. The semiconductor device according to claim 7 , wherein the first address output signals and the second address output signals output from the first to third memory chips are transmitted to the second to fourth memory chips through first parts of the first to third vias, respectively.
10. The semiconductor device according to claim 9 , wherein the fourth memory chip further has at least two fourth vias extending through the fourth substrate in the first direction.
11. The semiconductor device according to claim 9 , wherein the fourth memory chip does not have a via extending through the fourth substrate in the first direction.
12. The semiconductor device according to claim 9 , wherein each of the third ones of the first to third logical circuits of the first to third memory chips activates its respective chip based on the second address output signal transmitted in its respective chip, a first chip enable signal, and a second chip enable signal received at its respective chip.
13. The semiconductor device according to claim 12 , wherein the first chip enable signal and the second chip enable signal received at the first to third memory chips are transmitted to the second to fourth memory chips through second parts of the first to third vias, respectively.
14. The semiconductor device according to claim 4 , wherein:
the first logical operation is an inversion operation, and
the second logical operation is an exclusive disjunction operation.
15. The semiconductor device according to claim 2 , wherein facing surfaces of adjacent ones of the stacked first to fourth memory chips contact with each other.
16. The semiconductor device according to claim 1 , further comprising:
a second dedicated chip stacked on the one surface of the first memory chip in the first direction, the second dedicated chip including at least one via extending in the first direction and connected to another one of the first vias, and the second dedicated chip comprising an interface chip including an interface circuit,
wherein the first memory chip and the second dedicated chip overlap when viewed in the first direction, and
wherein an output from the second dedicated chip is supplied to the another one of the first vias.
17. The semiconductor device according to claim 16 , wherein the one of the first vias is provided in a peripheral circuit area of the first memory chip.
18. The semiconductor device according to claim 1 , wherein the one of the first vias is provided in a peripheral circuit area of the first memory chip.
19. The semiconductor device according to claim 1 , wherein:
the first memory chip includes a first terminal connected to a first wiring layer, a second terminal connected to a second wiring layer, and a third terminal connected to a third wiring layer and a switching element,
the semiconductor device is configured to select the first memory chip by a first chip address selection method and a second chip address selection method,
the first chip address selection method comprises generating a logical value based on two address signals, each of the two address signals being received through a respective one of the first terminal and the second terminal, and
the second chip address selection method comprises generating a logical value based on one address signal other than the two address signals and a switching state of the switching element.