IP Library Granted Patent US 11,574,994
Granted Patent B2
US 11,574,994 · App. 17/211,035 · Granted Feb 7, 2023

Semiconductor device

Inventors: Masahiro Shimura (Yokohama, JP); Mitsuhiro Noguchi (Yokohama, JP)
Assignee: Kioxia Corporation
H01L28/24H01L23/5228H01L27/0629
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Quick Facts
Patent No.
US 11,574,994
App. No.
17/211,035
Granted
Feb 7, 2023
Kind
B2
Abstract

A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.

Claims (19)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a second conductivity-type second semiconductor layer on a first conductivity-type first semiconductor layer;

stacking a first insulating film, a semiconductor film doped with impurities and a second insulating film on a main surface of the second semiconductor layer;

patterning the second insulating film and the semiconductor film and remaining a part of the semiconductor film to form a resistor, and removing upper portions of the first insulating film and the second semiconductor layer on a periphery of the resistor to form an irregular shape on an upper surface of the second semiconductor layer;

filling a region with a third insulating film, the region having the second insulating film and the semiconductor film removed therefrom by being patterned;

forming a fourth insulating film on upper surfaces of the second insulating film and the third insulating film;

forming a via that extends from the upper surface of the fourth insulating film and reaches the second semiconductor layer and forming a wiring via that extends from the upper surface of the fourth insulating film and reaches the resistor; and

forming a terminal and a wire on the upper surface of the fourth insulating film, the terminal being electrically connected to an upper end of the via, and the wire being electrically connected to an upper end of the wiring via.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising stacking a new semiconductor film doped with impurities on an upper surface of the semiconductor film before forming the fourth insulating film.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein an irregular shape in which a depth of a recess is 100 nm to 600 nm is formed on an upper surface of the second semiconductor layer, and the resistor is formed above a protrusion of the upper surface of the second semiconductor layer.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein impurities are selectively implanted into a part of an upper portion of the first semiconductor layer to form the second semiconductor layer, and the second semiconductor layer is formed so that a periphery of a lower portion of the second semiconductor layer is surrounded by the first semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is formed with a film thickness of 13 nm to 50 nm.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor film is a polysilicon film doped with impurities and having a film thickness of 40 nm to 400 nm.

7. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

forming a single combined resistor by connecting a plurality of the resistors with one another; and

connecting the second semiconductor layer to any of the plurality of resistors electrically.

8. The method for manufacturing a semiconductor device according to claim 7 , wherein the plurality of resistors having a same shape and arranged periodically are connected with one another to form the combined resistor.

9. The method for manufacturing a semiconductor device according to claim 7 , wherein any of mutual connection points of the plurality of resistors and the second semiconductor layer are electrically connected to each other.

10. The method for manufacturing a semiconductor device according to claim 7 , wherein the combined resistor is formed by alternately connecting the resistors and wires disposed on an upper surface of an insulating film formed above the resistors.

Assignments (1)
CHANGE OF NAME Recorded Dec 13, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058962/0888 →
Priority Claims (2)
JP JP2019-048013 · Mar 15, 2019 · national
JP JP2019-111760 · Jun 17, 2019 · national
Continuity (2)
Division 16564709 · Sep 9, 2019
Related Publication 20210210592A1 · Jul 8, 2021