Controller that acquires status of nonvolatile memory and control method thereof
According to an embodiment, a memory system including: a semiconductor memory configured to store data, a memory controller configured to issue a first command to suspend a first operation to the semiconductor memory which is executing the first operation, wherein the memory controller is configured to prohibit the issuance of the first command until a time in which the first operation is executed passes a first threshold, acquire a status of the semiconductor memory which is executing the first operation, and update the first threshold to a second threshold in accordance with the status.
1. A method of controlling a nonvolatile memory, said method comprising:
issuing a first command to the nonvolatile memory, the first command requesting to execute a first operation; and
acquiring a status of the nonvolatile memory from the nonvolatile memory, the status distinguishing between a first state of the nonvolatile memory and a second state of the nonvolatile memory, wherein,
in the first state, the nonvolatile memory executes a process for the first operation, and
in the second state, the nonvolatile memory verifies a result of the process for the first operation.
2. The method according to claim 1 , further comprising:
determining, on the basis of the acquired status, a timing to issue a second command to the nonvolatile memory, the second command requesting to suspend the first operation.
3. The method according to claim 2 , further comprising:
determining a first threshold period as a threshold period during which the second command is not issued; and
updating the threshold period from the first threshold period to a second threshold period on the basis of the acquired status.
4. The method according to claim 3 , further comprising:
updating the threshold period on the basis of a length of a time for the status of the nonvolatile memory to change from the first state to the second state.
5. The method according to claim 1 , wherein
the first operation includes an erase operation to erase data stored in the nonvolatile memory,
in the first state, the nonvolatile memory executes an erase process, and
in the second state, the nonvolatile memory executes an erase-verify process.
6. The method according to claim 3 , wherein
the second threshold period is longer than the first threshold period.
7. The method according to claim 3 , further comprising:
after a time from the issuance of the first command passes the first threshold period, issuing the second command to the nonvolatile memory;
issuing a third command to the nonvolatile memory in which the first operation is suspended, the third command requesting to execute a second operation; and
issuing a fourth command to the nonvolatile memory after the second operation finishes, the fourth command requesting to resume the suspended first operation.
8. The method according to claim 7 , further comprising:
after updating the threshold period from the first threshold period to the second threshold period, until a time from the issuance of the fourth command passes the second threshold period, not issuing the first command to the nonvolatile memory.
9. The method according to claim 7 , wherein,
the first operation includes an erase operation to erase data stored in the nonvolatile memory, and
the second operation includes a read operation to read data stored in the nonvolatile memory.
10. The method according to claim 7 , wherein
the first command is issued to the nonvolatile memory when a time to output a result of the second operation to an external device is limited.
11. A controller for controlling a nonvolatile memory, the controller comprising:
a circuit configured to:
issue a first command to the nonvolatile memory, the first command requesting to execute a first operation; and
acquire a status of the nonvolatile memory from the nonvolatile memory, the status distinguishing between a first state of the nonvolatile memory and a second state of the nonvolatile memory, wherein,
in the first state, the nonvolatile memory executes a process for the first operation, and
in the second state, the nonvolatile memory verifies a result of the process for the first operation.
12. The controller according to claim 11 , wherein the circuit is further configured to determine, on the basis of the acquired status, a timing to issue a second command to the nonvolatile memory, the second command requesting to suspend the first operation.
13. The controller according to claim 12 , wherein the circuit is configured to:
determine a first threshold period as a threshold period during which the circuit does not issue the second command; and
update the threshold period from the first threshold period to a second threshold period on the basis of the acquired status.
14. The controller according to claim 13 , wherein the circuit is configured to update the threshold period on the basis of a length of a time for the status of the nonvolatile memory to change from the first state to the second state.
15. The controller according to claim 13 , wherein the circuit is further configured to:
after a time from the issuance of the first command passes the first threshold period, issue the second command to the nonvolatile memory;
issue a third command to the nonvolatile memory in which the first operation is suspended, the third command requesting to execute a second operation; and
issue a fourth command to the nonvolatile memory after the second operation finishes, the fourth command requesting to resume the suspended first operation.
16. The controller according to claim 15 , wherein the circuit is further configured to:
after updating the threshold period from the first threshold period to the second threshold period, until a time from the issuance of the fourth command passes the second threshold period, not issuing the first command to the nonvolatile memory.
17. The controller according to claim 15 , wherein
the first operation includes an erase operation to erase data stored in the nonvolatile memory, and
the second operation includes a read operation to read data stored in the nonvolatile memory.
18. A nonvolatile memory comprising:
a memory cell array and a circuit configured to:
transmit a status of the circuit to a controller in response to a request from the controller, the status distinguishing between a first state of the circuit and a second state of the circuit, wherein,
in the first state, the circuit executes a process for a first operation that has started to be executed before the circuit transmits the status of the circuit, and
in the second state, the circuit verifies a result of the process for the first operation.
19. The nonvolatile memory according to claim 18 , wherein
the first operation includes an erase operation to erase data stored in the memory cell array,
in the first state, the circuit executes an erase process, and
in the second state, the circuit executes an erase-verify process.
20. The nonvolatile memory according to claim 18 , wherein
the first operation includes an erase operation to erase data stored in the memory cell array, and
the circuit is further configured to:
suspend the first operation in response to a command requesting to suspend the first operation from the controller to the circuit; and
while the first operation is suspended, execute a process for a second operation that includes a read operation to read data stored in the memory cell array.