Semiconductor interconnection structure and methods of forming the same

1. A method for forming an interconnection structure, comprising:

forming a conductive layer over a dielectric layer;

forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the conductive layer, wherein the one or more openings separates the conductive layer into one or more portions;

forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the conductive layer;

forming a sacrificial layer in the one or more openings;

recessing the sacrificial layer so that at least a portion of the capping layer is exposed in the one or more openings;

forming a support layer on the recessed sacrificial layer in each of the one or more openings;

removing the sacrificial layer to form an air gap in each of the one or more openings;

forming a dielectric fill on the support layer;

recessing the conductive layer;

forming an etch stop layer on the recessed conductive layer, the capping layer, the support layer and the dielectric fill;

forming a dielectric material on the etch stop layer;

forming a contact opening through the dielectric material and the etch stop layer to expose a top surface of a portion of the conductive layer; and

forming a conductive feature in the contact opening.

2. The method of claim 1 , wherein recessing the conductive layer, comprising:

removing a hard mask layer of the conductive layer.

3. The method of claim 1 , before recessing the conductive layer, further comprising:

forming a metal oxide layer on the capping layer, the support layer and the dielectric fill.

4. The method of claim 3 , wherein forming the etch stop layer on the recessed conductive layer, the capping layer, the support layer and the dielectric fill, comprises:

forming the etch stop layer on the recessed conductive layer, the capping layer and the metal oxide layer.

5. The method of claim 1 , wherein forming the dielectric fill, comprises:

disposing the dielectric fill in the support layer; and

performing a planarization operation to remove a portion of the capping layer, the support layer and the dielectric fill, wherein the capping layer, the support layer and the dielectric fill substantially have a co-planar top surface.

6. The method of claim 5 , wherein a top surface of the recessed conductive layer is lower than the co-planar top surface of the capping layer, the support layer and the dielectric fill.

7. A method, comprising:

forming a dielectric layer having a first conductive feature disposed therein;

depositing a conductive layer over the dielectric layer and the first conductive feature;

patterning the conductive layer to form a first portion and a second portion of the conductive layer, wherein the first portion of the conductive layer is disposed over the first conductive feature, and the second portion of the conductive layer is disposed over the dielectric layer;

depositing a capping layer over the conductive layer and the dielectric layer, wherein the capping layer has a first portion, a second portion opposing the first portion, and a third portion connecting the first portion and the second portion, wherein the first portion of the capping layer is in contact with the first portion of the conductive layer, the second portion of the capping layer is in contact with the second portion of the conductive layer, and the third portion of the capping layer is in contact with the dielectric layer;

depositing a sacrificial layer over the capping layer to fill gaps around the first portion and the second portions of the conductive layer;

recessing the sacrificial layer to below a top surface of the conductive layer;

forming a support layer in contact with the first and second portions of the capping layer; and

depositing an etch stop layer over the second portion of the conductive layer, the second portion of the capping layer and the support layer.

8. The method of claim 7 , further comprising removing the sacrificial layer to form an air gap, wherein the air gap is disposed between the first portion of the conductive layer and the second portion of the conductive layer.

9. The method of claim 8 , further comprising:

depositing a dielectric fill over the air gap and in contact with the support layer.

10. The method of claim 9 , wherein the etch stop layer is further disposed over the dielectric fill.

11. The method of claim 9 , wherein a top surface of the first portion of the conductive layer is lower than a top surface of the dielectric fill, and a top surface of the second portion of the conductive layer is lower than a top surface of the dielectric fill.

12. The method of claim 7 , further comprising:

depositing a dielectric material disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer; and

forming a second conductive feature in the dielectric material in contact with the first portion of the conductive layer and the first portion of the capping layer.

13. The method of claim 12 , further comprising:

depositing a barrier layer disposed between the second conductive feature and the first portion of the conductive layer, and in contact with the second conductive feature, the first portion of the conductive layer and the first portion of the capping layer.

14. The method of claim 12 , wherein the second conductive feature is further in contact with the support layer.

15. A method, comprising:

forming a dielectric layer having a first conductive feature disposed therein;

depositing a conductive layer over the first conductive feature and the dielectric layer;

forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the conductive layer, wherein the one or more openings separates the conductive layer into one or more portions;

depositing a capping layer, wherein a sidewall of the capping layer is in contact with the conductive layer, and a bottom surface of the capping layer is in contact with the dielectric layer;

forming a sacrificial layer in lower portions of the one or more openings in the conductive layer, wherein a portion of the sidewall of the capping layer is exposed to the one or more openings;

depositing a support layer over the sacrificial layer, wherein the support layer is in contact with the sidewall of the capping layer;

removing the sacrificial layer to form an air gap is formed between the support layer and the capping layer;

depositing a dielectric fill over the air gap and in contact with the support layer;

depositing an etch stop layer over the conductive layer and the capping layer;

depositing a dielectric material disposed over the etch stop layer; and

forming a second conductive feature in the dielectric material, wherein the second conductive feature is in contact with the conductive layer and the capping layer.

16. The method of claim 15 , wherein depositing the conductive layer comprises:

depositing a glue layer over the dielectric layer having a first conductive feature;

depositing a conductive material layer over the glue layer; and

depositing a hard mask layer over the conductive material layer.

17. The method of claim 16 , further comprising:

selectively forming a blocking layer over the hard mask layer.

18. The method of claim 17 , further comprising:

depositing a metal oxide layer over the dielectric fill, the support layer, and the capping layer.

19. The method of claim 18 , further comprising removing the blocking layer and the hard mask layer to expose a top surface of the conductive material layer.

20. The method of claim 19 , wherein the top surface of the conductive material layer is lower than a top surface of the metal oxide layer.