IP Library › Granted Patent US 11,575,050

Granted Patent B2

US 11,575,050 · App. 17/222,011 · Granted Feb 7, 2023

Semiconductor structure having both gate-all-around devices and planar devices

Inventor: Jhon Jhy Liaw (Hsinchu County, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

H01L29/78696 H01L21/823807 H01L21/823857 H01L27/092 H01L29/42392 H01L29/775

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Quick Facts

Patent No.: US 11,575,050
App. No.: 17/222,011
Granted: Feb 7, 2023
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate. Gate dielectric layers of the GAA nanowire transistors and the GAA nanosheet transistors have substantially the same thickness which is smaller than the thickness of the gate dielectric layer of the planar devices. The channel width of the planar devices is greater than the channel width of the GAA nanosheet transistors, which is greater than the channel width of the GAA nanowire transistors.

Claims (34)

1. An integrated circuit, comprising:

a substrate;

first gate-all-around (GAA) transistors on the substrate, wherein each first GAA transistor includes vertically stacked multiple first channels, a first gate dielectric layer wrapping around the first channels, and a first gate electrode wrapping around the first gate dielectric layer; and

a first planar transistor on the substrate, wherein the first planar transistor includes a second channel, a second gate dielectric layer over the second channel, and a second gate electrode over the second gate dielectric layer,

wherein the second gate dielectric layer is thicker than the first gate dielectric layers, and a first width of the first channels is smaller than a second width of the second channel.

2. The integrated circuit of claim 1 , further comprising second GAA transistors, wherein each second GAA transistor includes vertically stacked multiple third channels, a third gate dielectric layer wrapping around the third channels, and a third gate electrode wrapping around the third gate dielectric layer, wherein a third width of the third channels is greater than the first width, and the first and the third gate dielectric layers have about same thickness.

3. The integrated circuit of claim 2 , wherein the first and the second GAA transistors are in a core area of the integrated circuit, and the first planar transistor is in an I/O area of the integrated circuit separate from the core area.

4. The integrated circuit of claim 2 , wherein a ratio of the third width to the first width is in a range of 1.3 to 10.

5. The integrated circuit of claim 1 , wherein each of the first GAA transistors has a gate length less than 20 nm and the first planar transistor has a gate length greater than 50 nm.

6. The integrated circuit of claim 1 , further comprising a second planar transistor, wherein the second planar transistor and the first GAA transistors are in a core area of the integrated circuit, and the first planar transistor is in an I/O area of the integrated circuit separate from the core area.

7. The integrated circuit of claim 6 , wherein the second planar transistor includes a third channel, a third gate dielectric layer over the third channel, and a third gate electrode over the third gate dielectric layer, wherein the first and the third gate dielectric layers have substantially a same thickness, wherein the second planar transistor is away from the first GAA transistors by at least four times a gate pitch of the first GAA transistors.

8. An integrated circuit, comprising:

a substrate;

gate-all-around (GAA) nanowire transistors on the substrate, each GAA nanowire transistor having vertically stacked multiple nanowire channels, a first gate dielectric layer wrapping around the nanowire channels, and a first gate electrode wrapping around the first gate dielectric layer; and

GAA nanosheet transistors on the substrate, each GAA nanosheet transistor having vertically stacked multiple nanosheet channels, a second gate dielectric layer wrapping around the nanosheet channels, and a second gate electrode wrapping around the second gate dielectric layer; and

a first planar transistor on the substrate, the first planar transistor having a third channel, a third gate dielectric layer over the third channel, and a third gate electrode over the third gate dielectric layer,

wherein the first and the second gate dielectric layers have substantially a same thickness, and the third gate dielectric layer is thicker than both the first and the second gate dielectric layers, wherein a first width of the nanowire channels is smaller than a second width of the nanosheet channels, and the second width is smaller than a third width of the third channel, and wherein the GAA nanowire transistors and the GAA nanosheet transistors are adjacent to each other in a core area of the integrated circuit, and the first planar transistor is in an I/O area of the integrated circuit separate from the core area.

9. The integrated circuit of claim 8 , wherein a ratio of the second width to the first width is in a range of 1.3 to 10.

10. The integrated circuit of claim 8 , wherein the first width is equal to or less than 20 nm, the second width is equal to or less than 60 nm, and the third width is greater than 60 nm.

11. The integrated circuit of claim 8 , wherein each of the GAA nanowire transistors and the GAA nanosheet transistors has a gate length less than 20 nm and the first planar transistor has a gate length greater than 50 nm.

12. The integrated circuit of claim 8 , wherein each of the first and the second gate dielectric layers has a thickness less than 2.5 nm, and the third gate dielectric layer has a thickness greater than 3 nm.

13. The integrated circuit of claim 8 , wherein each of the nanowire channels and the nanosheet channels has a thickness in a range of 3 nm to 8 nm, the first width is in a range of 4 nm to 11 nm, the second width is in a range of 12 nm to 40 nm, and the third width is in a range of 60 nm to 3,000 nm.

14. The integrated circuit of claim 8 , further comprising a second planar transistor in the core area, the second planar transistor having a fourth channel, a fourth gate dielectric layer over the fourth channel, and a fourth gate electrode over the fourth gate dielectric layer, wherein the first, the second, and the fourth gate dielectric layers have substantially a same thickness, wherein the second planar transistor is away from the GAA nanosheet transistors and the GAA nanowire transistors by at least four times a gate pitch of the GAA nanosheet transistors, at least four times a gate pitch of the GAA nanowire transistors, at least four times a channel pitch of the GAA nanosheet transistors, or at least four times a channel pitch of the GAA nanowire transistors.

15. The integrated circuit of claim 14 , wherein a fourth width of the fourth channel is greater than the second width, and a gate length of the second planar transistor is at least twice of a gate length of the GAA nanowire transistors or the GAA nano sheet transistors.

16. The integrated circuit of claim 15 , wherein the fourth width is in a range of 60 nm to 3,000 nm.

17. An integrated circuit, comprising:

a substrate;

first gate-all-around (GAA) transistors on the substrate, each first GAA transistor having vertically stacked multiple first channels, a first gate dielectric layer wrapping around the first channels, and a first gate electrode wrapping around the first gate dielectric layer;

second GAA transistors on the substrate, each second GAA transistor having vertically stacked multiple second channels, a second gate dielectric layer wrapping around the second channels, and a second gate electrode wrapping around the second gate dielectric layer; and

18. The integrated circuit of claim 17 , wherein the first and the second GAA transistors are in a core area of the integrated circuit, and the first planar transistor is in an I/O area of the integrated circuit separate from the core area.

19. The integrated circuit of claim 18 , further comprising a second planar transistor in the core area, the second planar transistor having a fourth channel, a fourth gate dielectric layer over the fourth channel, and a fourth gate electrode over the fourth gate dielectric layer, wherein the first, the second, and the fourth gate dielectric layers have substantially a same thickness.

20. The integrated circuit of claim 19 , wherein the second planar transistor is away from the first and the second GAA transistors by at least four times a gate pitch of the first GAA transistors, at least four times a gate pitch of the second GAA transistors, at least four times a channel pitch of the first GAA transistors, or at least four times a channel pitch of the second GAA transistors.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2021

From: LIAW, JHON JHY

To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Reel/Frame 055821/0152 →

Continuity (2)

Division 16393166 · Apr 24, 2019

Related Publication 20210226070A1 · Jul 22, 2021