Systems and methods for delta-sigma digitization
A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.
1. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment the sampled analog signal into a plurality of separate data pipelines; a delta-sigma analog-to-digital converter (ADC) having a processor and a memory, and wherein the memory contains computer-executable instructions that, when executed by the processor, cause the delta-sigma ADC to implement a delta-sigma algorithm configured to individually quantize a respective signal segment contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
2. The interface of claim 1 , wherein the delta-sigma ADC comprises a field programmable gate array (FPGA).
3. The interface of claim 2 , wherein the predetermined number of quantization bits is one, and wherein the delta-sigma ADC is further configured to perform one-bit quantization according to a binary quantization protocol.
4. The interface of claim 1 , wherein the binary quantization protocol comprises on-off keying.
5. The interface of claim 2 , wherein the sampling unit comprises an FPGA mezzanine card (FMC).
6. The interface of claim 5 , wherein the FMC is configured to sample the input analog carrier signal at 5 GSa/s.
7. The interface of claim 6 , further comprising an input buffer logically disposed between the segmentation unit and the delta-sigma ADC.
8. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment and distribute contiguous data portions of the sampled analog signal in sequential order into a plurality of separate data pipelines, respectively; a delta-sigma analog-to-digital converter (ADC) configured to individually quantize a respective data portion contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
9. The interface of claim 7 , wherein the input buffer comprises an input first-in-first-out unit (FIFO) for each of the plurality of data pipelines.
10. The interface of claim 9 , wherein the input FIFO utilizes at least 10-bits to store each sample of the sampled analog signal in the input buffer.
11. The interface of claim 10 , wherein the input FIFO is configured to store W samples, where W represents a positive integer, wherein the input FIFO has a size of at least IOW bits, and wherein each of the W samples is stored in a 10-bit buffer.
12. The interface of claim 8 , further comprising an output buffer including a separate output first-in-first-out unit (FIFO) for each of the plurality of data pipelines.
13. The interface of claim 12 , wherein the output FIFO utilizes at least 1-bit to store segments of the sampled analog signal in the output buffer.
14. The interface of claim 13 , further comprising an input FIFO, wherein a size of the output FIFO is one tenth of the size of the input FIFO.
15. The interface of claim 7 , wherein a clock rate of the FPGA for each of the plurality of data pipelines is approximately 156.25 MHz or less.
16. The interface of claim 2 , wherein the FPGA is disposed within a distributed unit (DU) of a communication network.
17. The interface of claim 1 , wherein the input analog signal comprises at least one of a 5G new radio (5GNR) signal and a long term evolution (LTE) signal.
18. A method of optimizing a delta-sigma analog-to-digital converter (ADC) architecture for a field programmable gate array (FPGA), comprising the steps of: simulating a performance of the delta-sigma ADC according to a first floating-point calculation using floating-point coefficients of the delta-sigma ADC; approximating key coefficients from a floating-point format to a fixed-point format; performing a second floating-point calculation of the delta-sigma ADC performance using the approximated key fixed-point coefficients; performing a first fixed-point calculation of the delta-sigma ADC performance for a continuous input data stream using fixed-point coefficients obtained from performance of the second floating-point calculation; and performing a second fixed-point calculation of the delta-sigma ADC performance, wherein the continuous input data stream is segmented into a plurality of separate data blocks, and wherein the second fixed-point calculation is individually performed on each separate segmented data block.
19. The method of claim 18 , wherein the steps of performing the first and second fixed-point calculations are individually repeated until a calculated degradation of the delta-sigma ADC performance is within a predetermined acceptable value.
20. The method of claim 18 , wherein the logical structure comprises a pipeline architecture, and further comprising, a step of determining whether the operational speed of each pipeline in the pipeline architecture meets an operational speed time constraint of the FPGA.