High-density memory device with planar thin film transistor (TFT) selector and methods for making the same
A memory device and method of making the same, the memory device including bit lines disposed on the substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.
1. A memory device comprising:
a substrate;
a first memory structure layer comprising:
bit lines disposed on the substrate;
memory cells disposed on the bit lines;
a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells;
a second dielectric layer disposed on the first dielectric layer;
thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and
word lines disposed on the second dielectric layer and electrically connected to the TFTs.
2. The memory device of claim 1 , wherein the selector layers comprise:
channel layers disposed on the source and drain electrodes and comprising channel regions; and
high dielectric constant (high-k) dielectric layers disposed on the channel layers.
3. The memory device of claim 2 , wherein the word lines overlap with the channel regions.
4. The memory device of claim 2 , wherein each channel region is disposed between a corresponding pair of the source and drain lines.
5. The memory device of claim 2 , wherein each of the channel layer and the high-k dielectric layer continuously extend to cover at least two of the bit lines.
6. The memory device of claim 2 , wherein the channel layers comprise amorphous silicon or a semiconducting oxide.
7. The memory device of claim 2 , wherein the channel layers comprise a semiconducting oxide chosen from InGaZnO, InWO, InZnO, InSnO, GaOx, or InOx.
8. The memory device of claim 1 , wherein the memory cells are disposed between the TFTs and the substrate.
9. The memory device of claim 1 , wherein each word line is electrically connected to at least two of the TFTs.
10. The memory device of claim 1 , wherein the memory cells are not electrically connected to control elements formed in the substrate.
11. The memory device of claim 1 , wherein the memory cells and the TFTs are formed on an interconnect structure formed on the substrate.
12. The memory device of claim 11 , wherein:
the substrate is a semiconductor substrate including complementary metal-oxide-semiconductor transistors; and
the first memory structure layer is formed in a back-end-of-line (BEOL) process.
13. The memory device of claim 1 , further comprising at least two additional memory structure layers disposed on the first memory structure layer.
14. The memory device of claim 1 , wherein the memory cells are arranged over the substrate in an array.
15. The memory device of claim 1 , wherein the selector layers overlap with the drain lines and the drain lines overlap with the memory cells.
16. The memory device of claim 1 , wherein the memory cells comprise a magnetoresistive random-access memory (MRAM) cell, a resistive random-access memory (RRAM) cell, a ferroelectric random-access memory (FeRAM) cell, a phase-change random-access memory (PCRAM cell), or a combination thereof.
17. A memory device comprising:
a substrate;
a first memory structure layer comprising:
bit lines disposed on the substrate;
memory cells disposed on the bit lines;
a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells;
a second dielectric layer disposed on the first dielectric layer;
thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells; and
word lines disposed on the second dielectric layer and electrically connected to the TFTs; and
a second memory structure layer disposed on the first memory structure layer, the second memory structure layer comprising:
a third dielectric layer disposed on the first memory structure;
second bit lines embedded in the third dielectric layer;
second memory cells disposed on the second bit lines;
a fourth dielectric layer disposed on the third dielectric layer;
second TFTs embedded in the fourth dielectric layer and configured to selectively provide electric power to corresponding second memory cells; and
second word lines disposed on the fourth dielectric layer and electrically connected to the second TFTs.
18. The memory device of claim 17 , wherein the third dielectric layer extends between the word lines and the second bit lines.
19. The memory device of claim 17 , wherein the TFTs comprise drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines.
20. A memory device comprising:
a substrate;
a bit line disposed on the substrate;
a memory cell disposed on the bit line;
a first dielectric layer disposed on the substrate, surrounding the bit line and the memory cell;
a second dielectric layer disposed on the first dielectric layer;
a thin film transistor (TFT) embedded in the second dielectric layer and configured to selectively provide electric power to the memory cell; and
a word line disposed on the second dielectric layer and electrically connected to the TFT.