IP Library Granted Patent US 12,412,835
Granted Patent B2
US 12,412,835 · App. 17/241,374 · Granted Sep 9, 2025

Back-side power delivery with glass support at the front

Inventors: Abhishek A. Sharma (Hillsboro, OR); Wilfred Gomes (Portland, OR); Telesphor Kamgaing (Chandler, AZ)
Assignee: Intel Corporation
H01L23/5286H01L21/768H01L23/15H01L25/16
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Quick Facts
Patent No.
US 12,412,835
App. No.
17/241,374
Granted
Sep 9, 2025
Kind
B2
Abstract

Embodiments of the present disclosure are based on using transistors with back-side contacts. Such transistors enable back-side power delivery to IC components (e.g., transistors, etc.) of an IC structure, which may be more advantageous than front-side power delivery in some implementations. Embodiments of the present disclosure are further based on recognition that using a glass support structure at the front side of an IC structure with back-side power delivery may advantageously reduce parasitic effects in the IC structure, e.g., compared to using a silicon-based support structure at the front.

Claims (61)

1. An integrated circuit (IC) assembly, comprising:

a front end of line (FEOL) layer, comprising a plurality of FEOL devices;

a back-side power delivery structure, comprising a plurality of power interconnects coupled to various of the plurality of FEOL devices;

a back end of line (BEOL) layer, comprising a plurality of BEOL interconnects coupled to one or more of the plurality of FEOL devices, wherein the plurality of BEOL interconnects includes a first BEOL interconnect and a second BEOL interconnect;

a glass support structure comprising a thin-film device having a first terminal coupled to the first BEOL interconnect and having a second terminal coupled to the second BEOL interconnect; and

a bonding interface between the BEOL layer and the glass support structure,

wherein:

the FEOL layer is between the back-side power delivery structure and the BEOL layer,

the BEOL layer is between the FEOL layer and the glass support structure, and

at least a portion of the thin-film device extends through the bonding interface.

2. The IC assembly according to claim 1 , wherein the thin-film device is one of a resistor, a capacitor, or an inductor.

3. The IC assembly according to claim 1 , wherein the bonding interface includes oxygen.

4. The IC assembly according to claim 1 , wherein:

the plurality of FEOL devices includes a FEOL transistor having a source region and a drain region, and

at least one power interconnect of the plurality of power interconnects is coupled to the source region or the drain region.

5. The IC assembly according to claim 1 , wherein the back-side power delivery structure includes an insulator material enclosing at least portions of the plurality of power interconnects.

6. The IC assembly according to claim 1 , wherein the BEOL layer includes one or more memory layers, the one or more memory layers including memory cells comprising thin-film transistors.

7. The IC assembly according to claim 1 , further comprising:

a conductive interconnect extending through the bonding interface,

wherein the first terminal of the thin-film device is coupled to the first BEOL interconnect via the conductive interconnect.

8. The IC assembly according to claim 1 , wherein the bonding interface is a hybrid bonding interface.

9. The IC assembly according to claim 1 , further comprising a layer that includes a plurality of IC devices and interconnects, wherein:

the layer is between the glass support structure and the bonding interface,

the bonding interface is between the layer and the BEOL layer, and

at least one of the plurality of IC devices and interconnects of the layer is coupled to one or more of the plurality of BEOL interconnects.

10. The IC assembly according to claim 9 , wherein the bonding interface includes:

portions in contact with one or more portions of the layer, and

portions in contact with one or more portions of the BEOL layer.

11. The IC assembly according to claim 9 , wherein:

a cross-section of each of at least one interconnect of the layer and at least one interconnect of the BEOL interconnects is substantially a trapezoid that includes two parallel sides, one of which is a short side and another one of which is a long side,

for the trapezoid of the at least one interconnect of the layer, the short side is closer to the glass support structure than the long side, and

for the trapezoid of the at least one interconnect of the BEOL interconnects, the long side is closer to the glass support structure than the short side.

12. The IC assembly according to claim 11 , wherein:

a cross-section of at least one interconnect of the power interconnects is a trapezoid that includes two parallel sides, one of which is a short side and another one of which is a long side, and

for the trapezoid of the at least one interconnect of the power interconnects, the short side is closer to the glass support structure than the long side.

13. An integrated circuit (IC) assembly, comprising:

a first layer, comprising a plurality of transistors;

a power delivery structure, comprising a plurality of power interconnects coupled to at least one of the transistors;

a second layer, comprising a plurality of conductive interconnects coupled to one or more of the plurality of transistors, wherein the first layer is between the power delivery structure and the second layer;

a glass structure comprising a device having a terminal coupled to at least one of the plurality of interconnects; and

a bonding interface between the second layer and the glass structure,

wherein:

the at least one of the plurality of interconnects extends through the bonding interface, or

the terminal of the device is coupled to the at least one of the plurality of interconnects via a conductive interconnect that extends through the bonding interface.

14. The IC assembly according to claim 13 , wherein the device is one of a transistor, a memory cell, a resistor, a capacitor, an inductor.

15. The IC assembly according to claim 13 , wherein the bonding interface includes oxygen.

16. An integrated circuit (IC) assembly, comprising:

a first layer comprising a plurality of devices, wherein the plurality of devices include transistors or memory cells;

an interconnect structure comprising a plurality of conductive interconnects coupled to one or more of the plurality of devices;

a second layer comprising a first conductive interconnect and a second conductive interconnect;

a glass layer comprising a device having a first terminal coupled to the first conductive interconnect and having a second terminal coupled to the second conductive interconnect;

a bonding interface between the second layer and the glass layer; and

a third conductive interconnect extending through the bonding interface,

wherein:

the first layer is between the interconnect structure and the second layer,

the second layer is between the first layer and the glass layer, and

the first terminal of the device is coupled to the first conductive interconnect via the third conductive interconnect.

17. The IC assembly according to claim 16 , wherein at least a portion of the device extends through the bonding interface.

18. The IC assembly according to claim 16 , wherein the device is one of a transistor, a memory cell, a resistor, a capacitor, an inductor.

19. The IC assembly according to claim 16 , wherein the bonding interface is a hybrid bonding interface.

20. The IC assembly according to claim 16 , wherein the bonding interface includes oxygen.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2021
From: SHARMA, ABHISHEK A.; GOMES, WILFRED; KAMGAING, TELESPHOR
To: INTEL CORPORATION
Reel/Frame 056052/0094 →
Continuity (1)
Related Publication 20220344262A1 · Oct 27, 2022
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