Access transmission gate
Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
1. An apparatus, comprising:
a transmission gate, wherein the transmission gate includes:
an n-type back-end transistor; and
a p-type back-end transistor in parallel with the n-type back-end transistor.
2. The apparatus of claim 1 , wherein the transmission gate is on a non-silicon substrate.
3. The apparatus of claim 2 , wherein the transmission gate is over a logic element.
4. The apparatus of claim 1 , wherein the transmission gate includes:
a second gate;
a p-type semiconducting layer over the second gate;
an n-type semiconducting layer over the p-type semiconducting layer;
a bit line over the n-type semiconducting layer;
a first gate over the n-type semiconducting layer; and
a source line over the n-type semiconducting layer.
5. The apparatus of claim 4 , wherein a dielectric is between the second gate and the p-type semiconducting layer.
6. The apparatus of claim 4 , wherein a dielectric insulates the first gate from the bit line, source line, and the n-type semiconducting layer.
7. The apparatus of claim 1 , wherein the transmission gate is coupled to a memory element.
8. The apparatus of claim 7 , wherein the memory element is resistive random access memory (RRAM).
9. A computing device, comprising:
a memory device including a memory element coupled to a transmission gate, wherein the transmission gate includes:
an n-type back-end transistor; and
a p-type back-end transistor in parallel with the n-type back-end transistor.
10. The computing device of claim 9 , wherein the transmission gate is on a non-silicon substrate.
11. The computing device of claim 9 , wherein the transmission gate is over a logic element.
12. The computing device of claim 9 , wherein the transmission gate includes:
a second gate;
a p-type semiconducting layer over the second gate;
an n-type semiconducting layer over the p-type semiconducting layer;
a bit line over the n-type semiconducting layer;
a first gate over the n-type semiconducting layer; and
a source line over the n-type semiconducting layer.
13. The computing device of claim 9 , wherein the memory element is resistive random access memory (RRAM).
14. An integrated circuit (IC) die, comprising:
a non-silicon substrate;
a transmission gate on top of the non-silicon substrate, wherein the transmission gate includes:
an n-type back-end transistor; and
a p-type back-end transistor in parallel with the n-type back-end transistor.
15. The IC die of claim 14 , wherein the transmission gate is over a logic element.
16. The IC die of claim 14 , wherein the transmission gate includes:
a second gate;
a p-type semiconducting layer over the second gate;
an n-type semiconducting layer over the p-type semiconducting layer;
a bit line over the n-type semiconducting layer;
a first gate over the n-type semiconducting layer; and
a source line over the n-type semiconducting layer.
17. The IC die of claim 14 , wherein the transmission gate is coupled to a memory element.
18. The IC die of claim 17 , wherein the memory element is resistive random access memory (RRAM).