IP Library › Granted Patent US 7,696,063
Granted Patent B2
US 7,696,063 · App. 12/325,458 · Granted Apr 13, 2010

Manufacturing method of semiconductor device

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 7,696,063
App. No.
12/325,458
Granted
Apr 13, 2010
Kind
B2
Abstract

A semiconductor device which has higher integration and is further reduced in thickness and size. A semiconductor device with high performance and low power consumption. A semiconductor element layer separated from a substrate by using a separation layer is stacked over a semiconductor element layer formed by using another substrate and covered with a flattened inorganic insulating layer. After separation of the semiconductor element layer in a top layer from the substrate, the separation layer is removed so that an inorganic insulating film formed under the semiconductor element layer is exposed. The flattened inorganic insulating layer and the inorganic insulating film are made to be in close contact and bonded to each other. In addition, a semiconductor layer included in the semiconductor element layer is a single crystal semiconductor layer which is separated from a semiconductor substrate and transferred to a formation substrate.

Claims (92)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first inorganic insulating layer over the first substrate;

forming a first semiconductor element layer over the first inorganic insulating layer;

forming a second inorganic insulating layer over the first semiconductor element layer;

forming a separation layer over a second substrate;

forming a third inorganic insulating layer over the separation layer;

forming a second semiconductor element layer over the third inorganic insulating layer;

bonding a third substrate to the second semiconductor element layer;

exposing the third inorganic insulating layer by removing the separation layer and the second substrate;

bonding the second inorganic insulating layer and the third inorganic insulating layer to each other; and

forming a wiring layer for electrically connecting the first semiconductor element layer and the second semiconductor element layer.

2. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first separation layer over a first substrate;

forming a first inorganic insulating layer over the first separation layer;

forming a first semiconductor element layer over the first inorganic insulating layer;

forming a second inorganic insulating layer over the first semiconductor element layer;

forming a second separation layer over a second substrate;

forming a third inorganic insulating layer over the second separation layer;

forming a second semiconductor element layer over the third inorganic insulating layer;

bonding a third substrate to the second semiconductor element layer;

exposing the third inorganic insulating layer by removing the second separation layer and the second substrate;

bonding the second inorganic insulating layer and the third inorganic insulating layer to each other;

removing the third substrate from the second semiconductor element layer;

forming a wiring layer for electrically connecting the first semiconductor element layer and the second semiconductor element layer;

bonding a first flexible substrate to the second semiconductor element layer;

exposing the first inorganic insulating layer by removing the first separation layer and the first substrate; and

bonding a second flexible substrate to the first inorganic insulating layer.

3. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first weakened layer in a first single crystal semiconductor substrate;

forming a first inorganic insulating layer over the first substrate;

bonding the first single crystal semiconductor substrate to the first substrate with the first separation layer and the first inorganic insulating layer interposed between the first single crystal semiconductor substrate and the first substrate;

forming a first single crystal semiconductor layer over the first inorganic insulating layer by separating the first single crystal semiconductor substrate from the first substrate along the first weakened layer;

forming a first transistor using the first single crystal semiconductor layer over the first inorganic insulating layer;

forming a second inorganic insulating layer over the first transistor;

forming a second weakened layer in a second single crystal semiconductor substrate;

forming a separation layer over a second substrate;

forming a third inorganic insulating layer over the separation layer;

bonding the second single crystal semiconductor substrate to the second substrate with the separation layer and the third inorganic insulating layer interposed between the second single crystal semiconductor substrate and the second substrate;

forming a second single crystal semiconductor layer over the third inorganic insulating layer by separating the second single crystal semiconductor substrate from the second substrate along the second weakened layer;

forming a second transistor using the second single crystal semiconductor layer over the third inorganic insulating layer;

bonding a third substrate to the second transistor;

exposing the third inorganic insulating layer by removing the separation layer and the second substrate;

bonding the second inorganic insulating layer and the third inorganic insulating layer to each other; and

forming a wiring layer for electrically connecting the first transistor and the second transistor.

4. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first weakened layer in a first single crystal semiconductor substrate;

forming a first separation layer over a first substrate;

forming a first inorganic insulating layer over the first separation layer;

bonding the first single crystal semiconductor substrate to the first substrate with the first separation layer and the first inorganic insulating layer interposed between the first single crystal semiconductor substrate and the first substrate;

forming a first single crystal semiconductor layer over the first inorganic insulating layer by separating the first single crystal semiconductor substrate from the first substrate along the first weakened layer;

forming a first transistor using the first single crystal semiconductor layer over the first inorganic insulating layer;

forming a second inorganic insulating layer over the first transistor;

forming a second weakened layer in a second single crystal semiconductor substrate;

forming a second separation layer over a second substrate;

forming a third inorganic insulating layer over the second separation layer;

bonding the second single crystal semiconductor substrate to the second substrate with the second separation layer and the third inorganic insulating layer interposed between second single crystal semiconductor substrate and the second substrate;

forming a second single crystal semiconductor layer over the third inorganic insulating layer by separating the second single crystal semiconductor substrate from the second substrate along the second weakened layer;

forming a second transistor using the second single crystal semiconductor layer over the third inorganic insulating layer;

bonding a third substrate to the second transistor;

exposing the third inorganic insulating layer by removing the second separation layer and the second substrate;

bonding the second inorganic insulating layer and the third inorganic insulating layer to each other;

removing the third substrate from the second transistor;

forming a wiring layer for electrically connecting the first transistor and the second transistor;

bonding a first flexible substrate to the second transistor;

exposing the first inorganic insulating layer by removing the first separation layer and the first substrate; and

bonding a second flexible substrate to the first inorganic insulating layer.

5. A method for manufacturing a semiconductor device according to claim 1 , wherein each of the first substrate and the second substrate is a glass substrate.

6. A method for manufacturing a semiconductor device according to claim 2 , wherein each of the first substrate and the second substrate is a glass substrate.

7. A method for manufacturing a semiconductor device according to claim 3 , wherein each of the first substrate and the second substrate is a glass substrate.

8. A method for manufacturing a semiconductor device according to claim 4 , wherein each of the first substrate and the second substrate is a glass substrate.

9. A method for manufacturing a semiconductor device according to claim 1 , further comprising:

performing a plasma treatmenet to at least one of the second inorganic insulating layer and the third inorganic insulating layer before bonding the second inorganic insulating layer and the third inorganic insulating layer to each other.

10. A method for manufacturing a semiconductor device according to claim 2 , further comprising:

performing a plasma treatmenet to at least one of the second inorganic insulating layer and the third inorganic insulating layer before bonding the second inorganic insulating layer and the third inorganic insulating layer to each other.

11. A method for manufacturing a semiconductor device according to claim 3 , further comprising:

performing a plasma treatmenet to at least one of the second inorganic insulating layer and the third inorganic insulating layer before bonding the second inorganic insulating layer and the third inorganic insulating layer to each other.

12. A method for manufacturing a semiconductor device according to claim 4 , further comprising:

performing a plasma treatmenet to at least one of the second inorganic insulating layer and the third inorganic insulating layer before bonding the second inorganic insulating layer and the third inorganic insulating layer to each other.

13. A method for manufacturing a semiconductor device according to claim 1 , further comprising:

performing a flattening treatment to the second inorganic insulating layer.

14. A method for manufacturing a semiconductor device according to claim 2 , further comprising:

performing a flattening treatment to the second inorganic insulating layer.

15. A method for manufacturing a semiconductor device according to claim 3 , further comprising:

performing a flattening treatment to the second inorganic insulating layer.

16. A method for manufacturing a semiconductor device according to claim 4 , further comprising:

performing a flattening treatment to the second inorganic insulating layer.

17. A method for manufacturing a semiconductor device according to claim 1 , wherein the first semiconductor element layer comprises a transistor and the second semiconductor element layer comprises a memory element.

18. A method for manufacturing a semiconductor device according to claim 2 , wherein the first semiconductor element layer comprises a transistor and the second semiconductor element layer comprises a memory element.

19. A method for manufacturing a semiconductor device according to claim 1 , wherein the third substrate is a holding substrate.

20. A method for manufacturing a semiconductor device according to claim 2 , wherein the third substrate is a holding substrate.

21. A method for manufacturing a semiconductor device according to claim 3 , wherein the third substrate is a holding substrate.

22. A method for manufacturing a semiconductor device according to claim 4 , wherein the third substrate is a holding substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2008
From: TSUCHIYA, KAORU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 021904/0847 →
Priority Claims (1)
JP 2007-311910 · Dec 3, 2007 · national
Continuity (1)
Related Publication 20090142888A1 · Jun 4, 2009