Wiring structure having double capping structure, manufacturing method thereof, and integrated circuit chip having the same
A wiring structure includes a filling metal, a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal, a barrier metal on an outer surface of the first portion of the cover metal, and a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, wherein the filling metal has higher conductivity than the cover metal and the barrier metal.
1. A wiring structure, comprising:
a filling metal;
a cover metal including cobalt (Co) on the filling metal, the cover metal having:
a first portion along a side surface and along a lower surface of the filling metal, and
a second portion along an upper surface of the filling metal;
a barrier metal on an outer surface of the first portion of the cover metal; and
a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy,
wherein the filling metal has higher conductivity than the cover metal and the barrier metal,
wherein the second portion of the cover metal completely covers the upper surface of the filling metal, the first and second portions of the cover metal contacting each other to completely surround all outer surfaces of the filling metal, and
wherein an edge of the second portion of the cover metal extends beyond the first portion of the cover metal to directly contact an upper surface of the barrier metal.
2. The wiring structure as claimed in claim 1 , wherein the filling metal includes copper (Cu).
3. The wiring structure as claimed in claim 2 , wherein the cover metal consists of cobalt (Co).
4. The wiring structure as claimed in claim 1 , wherein the cobalt (Co) alloy includes cobalt (Co) and at least one of gold (Au), silver (Ag), tungsten (W), lead (Pb), and phosphorous (P).
5. The wiring structure as claimed in claim 1 , further comprising a top metal on an outer surface of the capping metal, the top metal including manganese (Mn).
6. The wiring structure as claimed in claim 1 , wherein:
the cover metal is directly on the filling metal; and
the barrier metal is directly on the first portion of the cover metal.
7. The wiring structure as claimed in claim 6 , wherein each of the cover metal and the barrier metal does not include manganese (Mn).
8. The wiring structure as claimed in claim 1 , wherein the first portion of the cover metal has a thickness of about 5 nm.
9. The wiring structure as claimed in claim 8 , wherein the second portion of the cover metal is thicker than the first portion of the cover metal.
10. The wiring structure as claimed in claim 1 , wherein oxygen contents (%) of the first and second portions of the cover metal are equal to each other.
11. The wiring structure as claimed in claim 1 , wherein an upper surface of the first portion of the cover metal is flat.
12. An integrated circuit chip, comprising:
a substrate;
a front-end-of-line (FEOL) structure on a first surface of the substrate, the FEOL structure including transistors; and
a back-end-of-line (BEOL) structure on the FEOL structure, the BEOL structure including a multilayer wiring structure and an interlayer insulating film insulating a part of the multilayer wiring structure, and the interlayer insulating film including sub-insulating films,
wherein at least one wiring of the multilayer wiring structure is in a trench, the trench being in one of the sub-insulating films of the interlayer insulating film, and the wiring including:
a filling metal in the trench, the filling metal including copper (Cu),
a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal,
a barrier metal on an outer surface of the first portion of the cover metal, while being directly on the trench,
a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, and
a top metal on the capping metal, the top metal including manganese (Mn),
wherein the second portion of the cover metal completely covers the upper surface of the filling metal, the first and second portions of the cover metal contacting each other to completely surround all outer surfaces of the filling metal, and
wherein an edge of the second portion of the cover metal extends beyond the first portion of the cover metal to directly contact an upper surface of the barrier metal.
13. The integrated circuit chip as claimed in claim 12 , wherein the cobalt (Co) alloy is a cobalt-tungsten-phosphorous (CoWP) alloy.
14. The integrated circuit chip as claimed in claim 12 , wherein a level of an upper surface of the second portion is higher than a level of an upper surface of the one sub-insulating film.