Integrated sensor with reduced skew
Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.
1. An integrated circuit, comprising:
a plurality of pixels, comprising:
a first pixel positioned in a row of the integrated circuit, comprising:
a first photodetection region configured to generate first charge carriers in response to incident photons, along an optical direction, from a light source;
a first charge storage region;
a first charge transfer channel configured to propagate at least some of the first charge carriers from the first photodetection region to the first charge storage region; and
a first transfer gate configured to bias the first charge transfer channel according to a control signal; and
a second pixel positioned in the row of the integrated circuit, comprising:
a second photodetection region configured to generate second charge carriers in response to incident photons, along the optical direction, from the light source;
a second charge storage region;
a second charge transfer channel configured to propagate at least some of the second charge carriers from the second photodetection region to the second charge storage region; and
a second transfer gate configured to bias the second charge transfer channel according to the control signal;
a first metal layer configured to receive, from a control circuit, the control signal, the first metal layer comprising a first portion elongated in a routing direction;
a second metal layer spaced from the first metal layer along an optical direction perpendicular to the routing direction and comprising a second portion configured to provide the control signal to the plurality of pixels, wherein the plurality of pixels are positioned along the routing direction; and
a plurality of vias coupling the first portion to the second portion along the optical direction and configured to transmit the control signal from the first portion of the first metal layer to the second portion of the second metal layer, each of the plurality of vias being longer in the routing direction than in a width direction that is perpendicular to the optical and routing directions,
wherein:
the first and second transfer gates are configured to receive the control signal via the first and second portions; and
in response to receiving the control signal, the first and second charge transfer channels are configured to conduct charge carriers to the first and second charge storage regions, respectively, within 0.75 nanoseconds of one another.
2. The integrated circuit of claim 1 , wherein the first portion is continuous along the routing direction and the second portion is continuous along the routing direction.
3. The integrated circuit of claim 1 , wherein the plurality of pixels is configured to receive incident photons from a light source along the optical direction.
4. The integrated circuit of claim 1 , wherein each of the plurality of pixels comprises a transfer gate configured to receive the control signal from the second portion of the second metal layer.
5. The integrated circuit of claim 4 , wherein each of the plurality of pixels further comprises a charge transfer channel coupled to the transfer gate and configured to propagate charge carriers and/or block propagation of charge carriers based on the control signal.
6. The integrated circuit of claim 5 , wherein each of the plurality of pixels further comprises a photodetection region and a charge storage region, and wherein the charge transfer channel electrically couples the photodetection region to the charge storage region.
7. The integrated circuit of claim 1 , further comprising a second integrated circuit comprising the control circuit, wherein the control circuit is coupled to the integrated circuit.
8. An integrated circuit, comprising:
a first pixel positioned in a row of the integrated circuit, comprising:
a first photodetection region configured to generate first charge carriers in response to incident photons, along an optical direction, from a light source;
a first charge storage region;
a first charge transfer channel configured to propagate at least some of the first charge carriers from the first photodetection region to the first charge storage region; and
a first transfer gate configured to bias the first charge transfer channel according to a control signal;
a second pixel positioned in the row of the integrated circuit, comprising:
a second photodetection region configured to generate second charge carriers in response to incident photons, along the optical direction, from the light source;
a second charge storage region;
a second charge transfer channel configured to propagate at least some of the second charge carriers from the second photodetection region to the second charge storage region; and
a second transfer gate configured to bias the second charge transfer channel according to the control signal;
a plurality of metal layers positioned above or below the first transfer gate in the optical direction and each extending in a routing direction perpendicular to the optical direction, the plurality of metal layers comprising first and second metal layers positioned consecutively in the optical direction; and
a plurality of vias extending in the optical direction and configured to transmit the control signal from a first continuous portion of the first metal layer to a second continuous portion of the second metal layer and spaced from one another in a width direction perpendicular to the routing and optical directions,
wherein:
each via is longer in the routing direction than in the width direction;
the first and second transfer gates are configured to receive the control signal via the first and second continuous portions; and
in response to receiving the control signal, the first and second charge transfer channels are configured to conduct charge carriers to the first and second charge storage regions, respectively, within 0.75 nanoseconds of one another.
9. The integrated circuit of claim 8 , wherein the plurality of metal layers further comprises a third metal layer and a fourth metal layer consecutively positioned in the optical direction.
10. The integrated circuit of claim 8 , wherein, in response to receiving the control signal, the first and second charge transfer channels are configured to conduct charge carriers to the first and second charge storage regions, respectively, within 0.5 nanoseconds of one another.
11. The integrated circuit of claim 8 , wherein, in response to receiving the control signal, the first and second charge transfer channels are configured to conduct charge carriers to the first and second charge storage regions, respectively, within 0.25 nanoseconds of one another.
12. The integrated circuit of claim 8 , wherein, in response to receiving the control signal, the first and second charge transfer channels are configured to conduct charge carriers to the first and second charge storage regions, respectively, within 0.1 nanoseconds of one another.