Integrated sensor with reduced skew
Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.
1. An integrated circuit, comprising:
first and second charge storage regions;
first and second charge transfer channels configured to propagate charge carriers to the first and second charge storage regions;
a first transfer gate configured to control, according to a control signal, a transfer of charge carriers to the first charge storage region via the first charge transfer channel, wherein the first transfer gate is configured to receive, at a first time having a first voltage, the control signal; and
a second transfer gate configured to control, according to the control signal, a transfer of charge carriers to the second charge storage region via the second charge transfer channel, wherein the second transfer gate is configured to receive, substantially at the first time having a second voltage different from the first voltage, the control signal,
wherein the first and second charge transfer channels have different first and second voltage thresholds, respectively.
2. The integrated circuit of claim 1 , further comprising:
a first pixel comprising:
a first photodetection region configured to generate first charge carriers in response to incident photons from a light source;
the first charge storage region; and
the first charge transfer channel, wherein the first charge transfer channel is configured to propagate at least some of the first charge carriers from the first photodetection region to the first charge storage region; and
a second pixel comprising:
a second photodetection region configured to generate second charge carriers in response to incident photons from the light source;
the second charge storage region; and
the second charge transfer channel, wherein the second charge transfer channel is configured to propagate at least some of the second charge carriers from the second photodetection region to the second charge storage region,
wherein the first and second pixels are positioned in a row of the integrated circuit.
3. The integrated circuit of claim 2 , further comprising:
a third pixel positioned in the row of the integrated circuit, the third pixel comprising:
a third photodetection region configured to generate third charge carriers in response to incident photons from the light source;
a third charge storage region; and
a third charge transfer channel configured to propagate at least some of the third charge carriers from the third photodetection region to the third charge storage region, the third charge transfer channel having a third voltage threshold that is different from the first and second voltage thresholds.
4. The integrated circuit of claim 2 , wherein the first pixel further comprises the first transfer gate, the first transfer gate being configured to bias the first charge transfer channel with the control signal and the second pixel further comprises the second transfer gate, the second transfer gate being configured to bias the second charge transfer channel with the control signal.
5. The integrated circuit of claim 4 , wherein:
the first voltage is greater than or equal to the first voltage threshold at the first transfer gate at the first time; and
the second voltage is greater than or equal to the second voltage threshold at the second transfer gate at the first time.
6. The integrated circuit of claim 5 , wherein a first length of the first charge transfer channel from the first photodetection region to the first charge storage region is different from a second length of the second charge transfer channel from the second photodetection region to the second charge storage region.
7. The integrated circuit of claim 5 , wherein:
the first charge transfer channel comprises a first doped portion configured to set the first voltage threshold, the first doped portion having a first length;
the second charge transfer channel comprises a second doped portion configured to set the second voltage threshold, the second doped portion having a second length different from the first length; and
the first and second doped portions have a first conductivity type, and the first and second charge storage regions have a second conductivity type opposite from the first conductivity type.
8. A method, comprising:
receiving, at a first transfer gate, at a first time having a first voltage, a control signal;
controlling, using the first transfer gate, according to the control signal, a transfer of charge carriers to a first charge storage region via a first charge transfer channel;
receiving, at a second transfer gate, substantially at the first time having a second voltage different from the first voltage, the control signal;
controlling, using the second transfer gate, according to the control signal, a transfer of charge carriers to a second charge storage region via a second charge transfer channel; and
propagating the charge carriers in the first and second charge transfer channels to the first and second charge storage regions,
wherein the first and second charge transfer channels have different first and second voltage thresholds, respectively.
9. The method of claim 8 , further comprising:
generating, in a first photodetection region of a first pixel that comprises the first charge storage region and the first charge transfer channel, in response to incident photons from a light source, first charge carriers, wherein propagating the charge carriers comprises propagating at least some of the first charge carriers in the first charge transfer channel from the first photodetection region to the first charge storage region; and
generating, in a second photodetection region of a second pixel that comprises the second charge storage region and the second charge transfer channel, in response to incident photons from a light source, second charge carriers, wherein propagating the charge carriers further comprises propagating at least some of the second charge carriers in the second charge transfer channel from the second photodetection region to the second charge storage region,
wherein the first and second pixels are positioned in a row of an integrated circuit.
10. The method of claim 9 , wherein:
the first pixel comprises the first transfer gate;
controlling the transfer of charge carriers to the first charge storage region using the first transfer gate comprises biasing the first charge transfer channel with the control signal;
the second pixel comprises the second transfer gate; and
controlling the transfer of charge carriers to the second charge storage region using the second transfer gate comprises biasing the second charge transfer channel with the control signal.
11. The method of claim 10 , wherein:
at the first time, the first voltage is greater than or equal to the first voltage threshold; and
at the first time, the second voltage is greater than or equal to the second voltage threshold.
12. The method of claim 11 , wherein a first length of the first charge transfer channel from the first photodetection region to the first charge storage region is different from a second length of the second charge transfer channel from the second photodetection region to the second charge storage region.
13. The method of claim 11 , wherein:
the first charge transfer channel comprises a first doped portion that sets the first voltage threshold, the first doped portion having a first length;
the second charge transfer channel comprises a second doped portion that sets the second voltage threshold, the second doped portion having a second length different from the first length; and
the first and second doped portions have a first conductivity type, and the first and second charge storage regions have a second conductivity type opposite from the first conductivity type.
14. The method of claim 9 , further comprising:
generating, in a third photodetection region of a third pixel positioned in the row of the integrated circuit, in response to incident photons from a light source, third charge carriers; and
propagating at least some of the third charge carriers in a third charge transfer channel from the third photodetection region to a third charge storage region of the third pixel, the third charge transfer channel having a third voltage threshold that is different from the first and second voltage thresholds.
15. An integrated circuit, comprising:
first and second drain regions;
first and second charge transfer channels configured to propagate charge carriers to the first and second drain regions;
a first transfer gate configured to control, according to a control signal, a transfer of charge carriers to the first drain region via the first charge transfer channel, wherein the first transfer gate is configured to receive, at a first time having a first voltage, the control signal; and
a second transfer gate configured to control, according to the control signal, a transfer of charge carriers to the second drain region via the second charge transfer channel, wherein the second transfer gate is configured to receive, substantially at the first time having a second voltage different from the first voltage, the control signal,
wherein the first and second charge transfer channels have different first and second voltage thresholds, respectively.
16. The integrated circuit of claim 15 , further comprising:
a first pixel comprising:
a first photodetection region configured to generate first charge carriers in response to incident photons from a light source;
the first drain region; and
the first charge transfer channel, wherein the first charge transfer channel is configured to propagate at least some of the first charge carriers from the first photodetection region to the first drain region; and
a second pixel comprising:
a second photodetection region configured to generate second charge carriers in response to incident photons from the light source;
the second drain region; and
the second charge transfer channel, wherein the second charge transfer channel is configured to propagate at least some of the second charge carriers from the second photodetection region to the second drain region,
wherein the first and second pixels are positioned in a row of the integrated circuit.
17. The integrated circuit of claim 16 , wherein:
the first voltage is greater than or equal to the first voltage threshold at the first transfer gate at the first time;
the first transfer gate is further configured to bias the first charge transfer channel with the control signal;
the second voltage is greater than or equal to the second voltage threshold at the second transfer gate at the first time; and
the second transfer gate is further configured to bias the second charge transfer channel with the control signal.
18. The integrated circuit of claim 17 , wherein a first length of the first charge transfer channel from the first photodetection region to the first drain region is different from a second length of the second charge transfer channel from the second photodetection region to the second drain region.
19. The integrated circuit of claim 17 , wherein:
the first charge transfer channel comprises a first doped portion configured to set the first voltage threshold, the first doped portion having a first length;
the second charge transfer channel comprises a second doped portion configured to set the second voltage threshold, the second doped portion having a second length different from the first length; and
the first and second doped portions have a first conductivity type, and the first and second charge storage regions have a second conductivity type opposite from the first conductivity type.