Method and system of manufacturing conductors and semiconductor device which includes conductors
A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
1. A system for manufacturing a semiconductor device, the system comprising:
at least one processor; and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating fin shapes, long axes of the fin shapes extending substantially parallel to a first direction;
generating first and second conductor shapes correspondingly over the fin shapes, long axes of the first and second conductor shapes extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction;
arranging a first sequence of alternating ones of the first and second conductor shapes relative to the first direction;
inserting a corresponding one of the second conductor shapes between each neighboring pair of corresponding ones of the first conductor shapes;
generating first, second, and third cap shapes correspondingly over the first and second conductor shapes, long axes of the first, second, and third cap shapes extending substantially parallel to the second direction;
generating first cut patterns over selected portions of corresponding ones of the first cap shapes and over corresponding portions of corresponding neighboring ones of the third cap shapes;
designating the first cut patterns as selective for a first etch sensitivity corresponding to the first cap shapes;
generating second cut patterns over selected portions of corresponding ones of the second cap shapes and over corresponding portions of corresponding neighboring ones of the third cap shapes; and
designating the second cut patterns as selective for a second etch sensitivity corresponding to the second cap shapes.
2. The system of claim 1 , further comprising at least one of:
a masking facility configured to fabricate one or more semiconductor masks based on based on the layout diagram; or
a fabricating facility configured to fabricate at least one component in a layer of a semiconductor device based on the layout diagram.
3. The system of claim 1 , wherein:
the generating first cut patterns includes:
extending spans of the first cut patterns over corresponding portions of corresponding neighboring ones of the third cap shapes; and
the generating second cut patterns includes:
extending spans of the second cut patterns over corresponding portions of corresponding neighboring ones of the third cap shapes.
4. The system of claim 1 , wherein:
the arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes results in:
first combinations of corresponding ones of the first cap shapes and corresponding ones of the first conductor shapes;
second combinations of corresponding ones of the second cap shapes and corresponding ones of the first conductor shapes;
third combinations of corresponding ones of the third cap shapes and corresponding ones of the second conductor shapes; and
the third combinations being interspersed with the first and second combinations.
5. The system of claim 1 , wherein the generating the layout diagram further includes:
designating the second conductor shapes as gate shapes which represent corresponding gate electrodes in the semiconductor device based on the layout diagram; and
designating the first conductor shapes as source/drain shapes which represent corresponding source/drain electrodes in a semiconductor device based on the layout diagram.
6. The system of claim 1 , wherein the generating the layout diagram further includes:
designating the first cut patterns as selective for a first etch sensitivity corresponding to the first cap shapes; and
designating the second cut patterns as selective for a second etch sensitivity corresponding to the second cap shapes.
7. The system of claim 6 , wherein the first etch sensitivity and the second etch sensitivity are represented correspondingly as ES 1 and ES 2 , and relate according to one of the following relation: 2*ES 1 ≤ES 2 .
8. The system of claim 1 , wherein the generating the layout diagram further includes:
generating transistor-channel shapes, long axes of the transistor-channel shapes extending substantially parallel to the second direction; and
disposing the transistor-channel shapes under corresponding ones of the first and second conductor shapes.
9. The system of claim 8 , wherein:
the transistor-channel shapes, are fin shapes which represent corresponding fin structures in a semiconductor device based on the layout diagram.
10. A system for manufacturing a semiconductor device, the system comprising:
at least one processor; and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating a base shape including parallel transistor-channel structure shapes arranged in a first direction;
generating first conductor shapes arranged parallel to a second direction and which are capped with corresponding first or second caps, each first cap having a first etch sensitivity, each second cap having a second etch sensitivity, the second direction being orthogonal to the first direction; and
generating second conductor shapes arranged parallel to and interspersed with the first conductor shapes and which are capped with third caps, each third cap having a third etch sensitivity; and
wherein:
the first conductor shapes are organized into at least first and second sets; and
the first, second and third etch sensitivities are different from each other.
11. The system of claim 10 , wherein:
the transistor-channel structure shapes are fin shapes;
the first conductor shapes are drain/source electrode shapes;
the second conductor shapes are gate electrode shapes; and
for a given region including corresponding sections of one or more of the fin shapes, a corresponding one of the gate electrode shapes and corresponding ones of drain/source electrode shapes represent components of a Fin-FET.
12. The system of claim 10 , wherein the first, second and third etch sensitivities are represented correspondingly as ES 1 , ES 2 and ES 3 and relate according to one of the following relations:
2*ES 1 ≤ES 2 and 2*ES 2 ≤ES 3 ;
2*ES 3 ≤ES 2 and 2*ES 2 ≤ES 1 ;
2*ES 3 ≤ES 1 and 2*ES 1 ≤ES 2 ; or
2*ES 2 ≤ES 3 and 2*ES 3 ≤ES 1 .
13. The system of claim 10 , wherein the base shape includes fin shapes arranged parallel to the first direction.
14. The system of claim 11 , wherein:
the first conductor shapes represent drain/source electrode shapes relative to corresponding regions of the fin shapes;
the second conductor shapes represent gate electrode shapes relative to corresponding regions of the fin shapes; and
wherein the drain/source electrode shapes and the gate electrode shapes are interspersed to provide Fin-FETs.
15. The system of claim 10 , further comprising at least one of:
a masking facility configured to fabricate one or more semiconductor masks based on based on the layout diagram; or
a fabricating facility configured to fabricate at least one component in a layer of a semiconductor device based on the layout diagram.
16. A system for manufacturing a semiconductor device, the system comprising:
at least one processor; and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating parallel transistor-channel structure shapes arranged in a first direction;
generating first conductor shapes arranged parallel to a second direction wherein the second direction is orthogonal to the first direction and wherein the first conductor shapes include:
a first set of the first conductor shapes which are each capped with a first cap having a first etch sensitivity;
a second set of the first conductor shapes which are each capped with a second cap having a second etch sensitivity;
second conductor shapes arranged parallel to and interspersed with the first conductor shapes and which are capped with third caps, each third cap having a third etch sensitivity; and
wherein the first, second and third etch sensitivities are different from each other.
17. The system of claim 16 , wherein:
the transistor-channel structure shapes are fin shapes;
the first set of the first conductor shapes are drain/source electrode shapes;
the second set of the first conductor shapes are other drain/source electrode shapes;
the second conductor shapes are gate electrode shapes; and
for a given region including corresponding sections of one or more of the fin shapes, a corresponding one of the gate electrode shapes and corresponding ones of drain/source electrode shapes represent components of a Fin-FET.
18. The system of claim 16 , further comprising at least one of:
a masking facility configured to fabricate one or more semiconductor masks based on based on the layout diagram; or
a fabricating facility configured to fabricate at least one component in a layer of a semiconductor device based on the layout diagram.
19. The system of claim 16 , wherein the first conductor shapes, including the first set and the second set, are substantially a same width.
20. The system of claim 16 , wherein the transistor-channel structure shapes include fins arranged parallel to the first direction.