Method of manufacturing conductors for semiconductor device
A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.
1. A method of manufacturing conductors for a semiconductor device, the method comprising:
forming active regions (ARs) in a first layer, the ARs extending in a first direction;
forming a conductive layer over the first layer;
forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other;
removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and
selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.
2. The method of claim 1 , wherein the forming a conductive layer includes:
using poly-silicon as a material comprising the conductive layer.
3. The method of claim 1 , wherein the forming active regions (ARs) includes:
forming fins that extend in the first direction.
4. The method of claim 3 , wherein:
the forming fins includes:
doping the fins to form drain/source regions representing first transistor-components, wherein second areas of the fins which are between corresponding drain/source regions are channel regions representing second transistor-components;
the gate electrodes are correspondingly over the channel regions and represent third transistor-components;
the first and second D/S electrodes are correspondingly over the drain/source regions and represent fourth transistor-components;
the forming fins and the removing portions of the conductive layer result in corresponding fin-type field-effect transistors (fin-FETs).
5. The method of claim 4 , wherein:
the forming fins and the removing portions of the conductive layer further result in corresponding transistors representing an inverter.
6. The method of claim 4 , wherein:
the forming fins and the removing portions of the conductive layer further result in corresponding transistors representing a multiplexer.
7. The method of claim 4 , wherein:
the forming fins and the removing portions of the conductive layer further result in corresponding transistors representing a buffer circuit.
8. The method of claim 1 , wherein the selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes includes:
protecting second D/S electrodes;
protecting first D/S electrodes; and
removing selected ones of first D/S electrodes and the second D/S electrodes.
9. The method of claim 8 , wherein:
the protecting second D/S electrodes includes:
forming first mask portions over the third caps of some of the second D/S electrodes to leave the third caps of selected ones of the second D/S electrodes exposed;
subjecting the exposed third caps to a first etchant which is selective for a first etch sensitivity to remove the exposed third caps correspondingly from the selected second D/S electrodes resulting in corresponding first gaps; and
removing the first mask portions; and
the protecting first D/S electrodes includes:
forming second mask portions over the second caps of some of the first D/S electrodes to leave the second caps of selected ones of first D/S electrodes exposed;
subjecting the exposed second caps to a second etchant which is selective for a second etch sensitivity to remove the exposed second caps correspondingly from the selected first D/S electrodes; and
removing the second mask portions.
10. The method of claim 9 , wherein:
the forming first mask portions includes:
extending spans of the first mask portions to cover some of the first caps of the gate electrodes; or
the forming second mask portions includes:
extending spans of the second mask portions to cover some of the first caps of the gate electrodes.
11. The method of claim 9 , wherein:
the forming first mask portions includes:
extending spans of the first mask portions to cover some of second caps of the first D/S electrodes; or
the forming second mask portions includes:
extending spans of the first mask portions to cover some of the first gaps.
12. The method of claim 9 , wherein:
for a third etchant which is selective for a third etch sensitivity (ES 1 ), the third etchant being usable to remove exposed ones of the first caps,
the thrid etch sensitivity (ES 1 ), the second etch sensitivity (ES 2 ) and the first etch sensitivity (ES 3 ) relate according to one of the following relations:
2*ES 1 ≤ES 2 and 2*ES 2 ≤ES 3 ;
2*ES 3 ≤ES 2 and 2*ES 2 ≤ES 1 ;
2*ES 3 ≤ES 1 and 2*ES 1 ≤ES 2 ; or
2*ES 2 ≤ES 3 and 2*ES 3 ≤ES 1 .
13. A method of manufacturing conductors for a semiconductor device, the method comprising:
forming active regions (ARs) in a first layer, the ARs extending in a first direction;
forming a conductive layer over the first layer;
forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other;
protecting unselected ones of the second caps;
removing selected ones of the second caps to expose correspondingly portions of the conductive layer;
protecting unselected ones of the third caps;
removing selected ones of the third caps to expose correspondingly portions of the conductive layer;
removing the exposed portions of the conductive layer resulting in correspondingly reduced quantities of capped first and capped second drain/source (D/S) electrodes; and
removing the first, second and third caps resulting in corresponding uncapped gate electrodes and uncapped first and uncapped second D/S electrodes.
14. The method of claim 13 , wherein:
the protecting unselected ones of the second caps includes:
forming first mask portions over the third caps of some of the capped second D/S electrodes to leave the third caps of selected ones of the capped second D/S electrodes exposed;
subjecting the exposed third caps to a first etchant which is selective for a first etch sensitivity to remove the exposed third caps correspondingly from the selected capped second D/S electrodes; and
removing the first mask portions; and
the protecting unselected ones of the third caps includes:
forming second mask portions over the second caps of some of the caped first D/S electrodes to leave the second caps of selected ones of capped first D/S electrodes exposed;
subjecting the exposed second caps to a second etchant which is selective for a second etch sensitivity to remove the exposed second caps correspondingly from the selected capped first D/S electrodes; and
removing the second mask portions.
15. The method of claim 14 , wherein, for capped gate electrodes correspondingy having the first caps formed thereover, at least some of the capped gate electrodes being precursors to the uncapped gate electrodes:
the forming first mask portions includes:
extending spans of the first mask portions to cover some of the first caps of the capped gate electrodes; or
the forming second mask portions includes:
extending spans of the second mask portions to cover some of the first caps of the capped gate electrodes.
16. The method of claim 14 , wherein:
the forming first mask portions includes:
extending spans of the first mask portions to cover some of second caps of the capped first D/S electrodes; or
the forming second mask portions includes:
extending spans of the first mask portions to cover some of the third caps of the capped second D/S electrodes.
17. A method of manufacturing conductors for a semiconductor device, the method comprising:
forming active regions (ARs) including fins in a first layer, the fins extending in a first direction, the forming active regions (ARs) including:
forming fins that extend in the first direction; and
doping the fins to form drain/source regions representing first transistor-components, wherein second areas of the fins which are between corresponding drain/source regions are channel regions representing second transistor-components;
forming a conductive layer over the first layer;
forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other;
selectively removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and
selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes;
the gate electrodes being correspondingly over the channel regions and representing third transistor-components;
the first and second D/S electrodes being correspondingly over the drain/source regions and representing fourth transistor-components; and
the forming fins and the selectively removing portions of the conductive layer resulting in corresponding fin-type field-effect transistors (fin-FETs).
18. The method of claim 17 , wherein:
the forming fins and the selectively removing portions of the conductive layer further result in corresponding transistors representing an inverter.
19. The method of claim 17 , wherein:
the forming fins and the selectively removing portions of the conductive layer further result in corresponding transistors representing a multiplexer.
20. The method of claim 17 , wherein:
the forming fins and the selectively removing portions of the conductive layer further result in corresponding transistors representing a buffer circuit.