Non-volatile semiconductor memory device and memory system

1. A non-volatile semiconductor memory device comprising:

a semiconductor substrate;

a source line provided above the semiconductor substrate

a bit line provided above the semiconductor substrate;

a first select gate line provided above the semiconductor substrate; and

a second select gate line provided above the semiconductor substrate,

a plurality of word lines stacked between the semiconductor substrate and the bit line;

a first semiconductor layer penetrating the first select gate line, the word lines and the second select gate line, and a charge accumulation layer provided between the first semiconductor layer and the first select gate line, between the first semiconductor layer and the word lines and between the first semiconductor layer and the second select gate line, the first semiconductor and the charge accumulation layer forming a first select transistor to a gate of which the first select gate line is connected, a plurality of memory cells to gates of which the word lines are connected, respectively and a second select transistor to a gate of which the second select gate line is connected; and

a control circuit configured to perform

an erase operation to bring threshold voltage levels of the memory cells below a first threshold voltage level,

first write operations to bring the threshold voltage levels of the memory cell above a second threshold voltage level, the first write operation being performed after the erase operation, the second threshold voltage level being higher than the first threshold voltage level, and

a second write operation to bring at least part of the threshold voltage levels of the memory cells above a third threshold voltage level, the second write operation being performed after the first write operation, the third threshold voltage level being higher than the second threshold voltage level,

wherein

the control circuit is further configured to

upon receipt of a suspend command during when the first write operation is being performed, suspend the first write operation,

upon receipt of a first command after the first write operation has been suspended, perform a first operation, and

upon receipt of a resume command after the first operation has been performed, resume the first write operation.

2. The non-volatile semiconductor memory device according to claim 1 , wherein

the control circuit

performs the erase operation and the first write operation upon receipt of an erase command,

suspends the first write operation upon receipt of the suspend command during when the first write operation is being performed,

performs the first operation upon receipt of the first command after the first write operation has been suspended,

resumes the first write operation upon receipt of the resume command after the first operation has been performed, and

performs the second write operation upon receipt of a write command after the first write operation has been performed.

3. The non-volatile semiconductor memory device according to claim 1 , wherein

the control circuit

performs the erase operation upon receipt of an erase command,

performs the first write operation upon receipt of a first write command after the erase operation has been performed,

suspends the first write operation upon receipt of the suspend command during when the first write operation is being performed,

performs the first operation upon receipt of the first command after the first write operation has been suspended,

resumes the first write operation upon receipt of the resume command after the first operation has been performed, and

performs the second write operation upon receipt of a second write command after the first write operation has been performed.

4. The non-volatile semiconductor memory device according to claim 1 , wherein

the first operation is an operation selected from a group, the group consisting of:

a read operation;

a write operation; and

a status information output operation.

5. The non-volatile semiconductor memory device according to claim 1 , further comprising

a storage portion configured to store interruption information,

wherein

the interruption information indicates a timing at which the first write operation is suspended, and

the control circuit resumes the first write operation based on the interruption information.

6. The non-volatile semiconductor memory device according to claim 5 , wherein

the control circuit transmits the interruption information to outside upon receipt of an inquiry command.

7. The non-volatile semiconductor memory device according to claim 1 , wherein

the first select transistor, the memory cells and the second select transistor form a memory string, and

the memory cells includes

a plurality of series-connected first memory cells one end of which is connected to the first select transistor, and

a plurality of series-connected second memory cells one end of which is connected to the second select transistor,

the memory string further includes a back gate transistor provided between the other end of the first memory cells and the other end of the second memory cells.

8. The non-volatile semiconductor memory device according to claim 1 , wherein

each of the memory cells is capable of storing 2 bits or more of data after the second write operation.

9. The non-volatile semiconductor memory device according to claim 1 , wherein

each of the memory cells is capable of storing 1 bit of data after the second write operation.

10. The non-volatile semiconductor memory device according to claim 2 , wherein

the first command is a command selected from a group consisting of a read command, the write command, and a status inquiry command,

the suspend command is different from the read command, the write command, the erase command, and the status inquire command, and

the resume command is different from the read command, the write command, the erase command, the status inquire command and the suspend command.

11. The non-volatile semiconductor memory device according to claim 1 , further including:

a tunnel insulating layer provided between the charge accumulation layer and the first select gate line, between the charge accumulation layer and the word lines and between the charge accumulation layer and the second select gate line; and

a block insulating layer provided between the first semiconductor layer and the charge accumulation layer.