IP Library Granted Patent US 11,536,904
Granted Patent B2
US 11,536,904 · App. 17/233,864 · Granted Dec 27, 2022

Optical dielectric waveguide structure

Inventors: William Ring (High Bridge, NJ); Miroslaw Florjanczyk (Kanata, CA)
G02B6/13G02B6/12028G02B6/423G02B6/4272G02B6/43G02B6/12016G02B6/12019G02B6/1223G02B6/421G02B6/4206G02B6/4224G02B6/4251G02B6/4274G02B2006/12061
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,536,904
App. No.
17/233,864
Granted
Dec 27, 2022
Kind
B2
Abstract

An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Claims (86)

1. A waveguide comprising

a stack of two or more SiON layers on a substrate,

wherein a functionality of the substrate is susceptible to be degraded at temperatures greater than 400 C,

wherein the two or more SiON layers comprise at least two layers having different indexes of refraction,

wherein the processes to completely form the waveguide are limited to temperatures less than or equal to 400 C; and

at least one of

one or more SiON bottom spacer layers disposed on the buffer layer,

one or more SiON top spacer layers disposed on the repeated stack, or

a SiON top layer disposed on the repeated stack.

2. A waveguide as in claim 1 , further comprising

a buffer layer comprising SiON on a substrate and under the stack of the two or more SiON layers.

3. A waveguide as in claim 1 ,

wherein the substrate comprises a material or an element that has a property changed at temperatures greater than 400 C, or

wherein the substrate comprises an interconnect layer that is susceptible to be damaged at temperatures greater than 400 C.

4. A waveguide as in claim 1 ,

wherein the substrate comprises a device fabricated thereon,

wherein the device or a connection element connected to the device is susceptible to be damaged at temperatures greater than 400 C.

5. A waveguide as in claim 1 ,

wherein the layers of the repeated stack comprise a stoichiometry of Si, O, and N to provide a stress having a magnitude less than or equal to 20 MPa.

6. A waveguide as in claim 5 ,

wherein the stoichiometry is configured to provide an index of refraction between 1.45 and 2.15 or between 1.6 and 2.05.

7. A waveguide as in claim 1 ,

wherein the stack comprises 3 to 20 pairs of SiON layers.

8. A waveguide as in claim 1 ,

wherein the overall total thickness of the stack is between 8 and 12 microns for a direct optical coupling with a core of an optical fiber.

9. An assembly comprising

a substrate;

an interconnection layer disposed on the substrate,

wherein the interconnection layer comprises at least an interconnection line,

wherein a component of the interconnect layer is susceptible to be degraded at temperatures greater than 400 C;

a waveguide on the interconnection layer,

wherein the waveguide comprises a stack of two or more SiON layers,

wherein the two or more SiON layers comprise at least two layers having different indexes of refraction,

wherein the processes to completely form the waveguide are limited to temperatures less than or equal to 400 C; and

a first device under the interconnection layer,

wherein a terminal of the first device is connected to a first interconnection line of the at least an interconnection line.

10. An assembly as in claim 9 , further comprising

a second device optically coupled to the waveguide,

wherein a terminal of the second device is connected to a second interconnection line of the at least an interconnection line.

11. An assembly as in claim 9 , further comprising

a high heat conduction layer for removing thermal energy from a second device formed coupling to the waveguide.

12. An assembly as in claim 9 , further comprising

a v-groove on the substrate for attaching an optical fiber coupled to the waveguide.

13. An assembly as in claim 9 ,

wherein the waveguide comprises a filter, an arrayed waveguide, a grating, a multiplexer, a demultiplexer, a spot size converter, or a power combiner.

14. An assembly as in claim 9 , further comprising

a buffer layer comprising SiON on the interconnection layer and under the stack of the two or more SiON layers.

15. An assembly comprising

a substrate;

a first device fabricated on the substrate;

an interconnection layer disposed on at least a part of the substrate,

wherein the interconnection layer comprises one or more interconnection lines,

wherein a first interconnection line of the one or more interconnection lines is connected to a first terminal of the first device,

wherein a component of the interconnect layer or the first device is susceptible to be degraded at temperatures greater than 400 C;

a waveguide on the interconnection layer,

wherein the waveguide comprises a stack of two or more SiON layers,

wherein the two or more SiON layers comprise at least two layers having different indexes of refraction,

wherein the processes to completely form the waveguide are limited to temperatures less than or equal to 400 C,

a second device directly or indirectly coupled to the waveguide,

wherein the second device comprises at least a second terminal,

wherein a second interconnection line of the one or more interconnection lines is connected to the second terminal.

16. An assembly as in claim 15 , further comprising

a cap disposed on the substrate for hermetically sealing the second device and a portion of the waveguide.

17. An assembly as in claim 15 , further comprising

a high heat conduction layer for removing thermal energy from the second device.

18. An assembly comprising

a substrate;

an interconnection layer disposed on the substrate,

wherein the interconnection layer comprises at least an interconnection line,

wherein a component of the interconnect layer is susceptible to be degraded at temperatures greater than 400 C;

a waveguide on the interconnection layer,

wherein the waveguide comprises a stack of two or more SiON layers,

wherein the two or more SiON layers comprise at least two layers having different indexes of refraction,

wherein the processes to completely form the waveguide are limited to temperatures less than or equal to 400 C; and

a device optically coupled to the waveguide,

wherein a terminal of the device is connected to the at least an interconnection line.

19. An assembly comprising

a substrate;

an interconnection layer disposed on the substrate,

wherein the interconnection layer comprises at least an interconnection line,

wherein a component of the interconnect layer is susceptible to be degraded at temperatures greater than 400 C;

a waveguide on the interconnection layer,

wherein the waveguide comprises a stack of two or more SiON layers,

wherein the two or more SiON layers comprise at least two layers having different indexes of refraction,

wherein the processes to completely form the waveguide are limited to temperatures less than or equal to 400 C; and

a high heat conduction layer for removing thermal energy from a device formed coupling to the waveguide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2023
From: RING, WILLIAM; FLORJANCZYK, MIROSLAW
To: POET TECHNOLOGIES, INC.
Reel/Frame 065460/0336 →
Continuity (4)
Continuation 16746824 · Jan 18, 2020
Continuation 16036151 · Jul 16, 2018
Provisional Application 62621659 · Jan 25, 2018
Related Publication 20210255386A1 · Aug 19, 2021